2 * Board initialization for EP93xx
5 * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
8 * Matthias Kaehlcke <matthias <at> kaehlcke.net>
10 * (C) Copyright 2002 2003
11 * Network Audio Technologies, Inc. <www.netaudiotech.com>
12 * Adam Bezanson <bezanson <at> netaudiotech.com>
14 * SPDX-License-Identifier: GPL-2.0+
21 #include <asm/arch/ep93xx.h>
23 DECLARE_GLOBAL_DATA_PTR;
26 * usb_div: 4, nbyp2: 1, pll2_en: 1
27 * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000,
28 * pll2_x2: 384000000.000000, pll2_out: 192000000.000000
30 #define CLKSET2_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
31 24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
32 24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
33 1 << SYSCON_CLKSET_PLL_PS_SHIFT | \
34 SYSCON_CLKSET2_PLL2_EN | \
35 SYSCON_CLKSET2_NBYP2 | \
36 3 << SYSCON_CLKSET2_USB_DIV_SHIFT)
38 #define SMC_BCR6_VALUE (2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \
39 SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \
40 1 << SMC_BCR_MW_SHIFT)
42 /* delay execution before timers are initialized */
43 static inline void early_udelay(uint32_t usecs)
45 /* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */
46 register uint32_t loops = (usecs * 1000) / 20;
48 __asm__ volatile ("1:\n"
50 "bne 1b" : "=r" (loops) : "0" (loops));
53 #ifndef CONFIG_EP93XX_NO_FLASH_CFG
54 static void flash_cfg(void)
56 struct smc_regs *smc = (struct smc_regs *)SMC_BASE;
58 writel(SMC_BCR6_VALUE, &smc->bcr6);
67 * Setup PLL2, PPL1 has been set during lowlevel init
69 struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
70 writel(CLKSET2_VAL, &syscon->clkset2);
73 * the user's guide recommends to wait at least 1 ms for PLL2 to
78 /* Go to Async mode */
79 __asm__ volatile ("mrc p15, 0, r0, c1, c0, 0");
80 __asm__ volatile ("orr r0, r0, #0xc0000000");
81 __asm__ volatile ("mcr p15, 0, r0, c1, c0, 0");
89 /* Machine number, as defined in linux/arch/arm/tools/mach-types */
90 gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
92 /* adress of boot parameters */
93 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
95 /* We have a console */
108 int board_early_init_f(void)
111 * set UARTBAUD bit to drive UARTs with 14.7456MHz instead of
114 struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
115 writel(SYSCON_PWRCNT_UART_BAUD, &syscon->pwrcnt);
119 int board_eth_init(bd_t *bd)
121 return ep93xx_eth_initialize(0, MAC_BASE);
124 static void dram_fill_bank_addr(unsigned dram_addr_mask, unsigned dram_bank_cnt,
125 unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS])
127 if (dram_bank_cnt == 1) {
128 dram_bank_base[0] = PHYS_SDRAM_1;
130 /* Table lookup for holes in address space. Maximum memory
131 * for the single SDCS may be up to 256Mb. We start scanning
132 * banks from 1Mb, so it could be up to 128 banks theoretically.
133 * We need at maximum 7 bits for the loockup, 8 slots is
134 * enough for the worst case.
137 unsigned i = dram_bank_cnt / 2;
138 unsigned j = 0x00100000; /* 1 Mb */
139 unsigned *ptbl = tbl;
141 while (!(dram_addr_mask & j)) {
149 for (i = dram_bank_cnt, j = 0;
150 (i != 0) && (j < CONFIG_NR_DRAM_BANKS); --i, ++j) {
151 unsigned addr = PHYS_SDRAM_1;
155 for (k = 0, bit = 1; k < 8; k++, bit <<= 1) {
160 dram_bank_base[j] = addr;
165 /* called in board_init_f (before relocation) */
166 static unsigned dram_init_banksize_int(int print)
169 * Collect information of banks that has been filled during lowlevel
173 unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS];
174 unsigned dram_total = 0;
175 unsigned dram_bank_size = *(unsigned *)
176 (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_SIZE);
177 unsigned dram_addr_mask = *(unsigned *)
178 (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_MASK);
179 unsigned dram_bank_cnt = *(unsigned *)
180 (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_COUNT);
182 dram_fill_bank_addr(dram_addr_mask, dram_bank_cnt, dram_bank_base);
184 for (i = 0; i < dram_bank_cnt; i++) {
185 gd->bd->bi_dram[i].start = dram_bank_base[i];
186 gd->bd->bi_dram[i].size = dram_bank_size;
187 dram_total += dram_bank_size;
189 for (; i < CONFIG_NR_DRAM_BANKS; i++) {
190 gd->bd->bi_dram[i].start = 0;
191 gd->bd->bi_dram[i].size = 0;
195 printf("DRAM mask: %08x\n", dram_addr_mask);
196 printf("DRAM total %u banks:\n", dram_bank_cnt);
197 printf("bank base-address size\n");
199 if (dram_bank_cnt > CONFIG_NR_DRAM_BANKS) {
200 printf("WARNING! UBoot was configured for %u banks,\n"
201 "but %u has been found. "
202 "Supressing extra memory banks\n",
203 CONFIG_NR_DRAM_BANKS, dram_bank_cnt);
204 dram_bank_cnt = CONFIG_NR_DRAM_BANKS;
207 for (i = 0; i < dram_bank_cnt; i++) {
208 printf(" %u %08x %08x\n",
209 i, dram_bank_base[i], dram_bank_size);
211 printf(" ------------------------------------------\n"
219 void dram_init_banksize(void)
221 dram_init_banksize_int(0);
224 /* called in board_init_f (before relocation) */
227 struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
228 unsigned sec_id = readl(SECURITY_EXTENSIONID);
229 unsigned chip_id = readl(&syscon->chipid);
231 printf("CPU: Cirrus Logic ");
232 switch (sec_id & 0x000001FE) {
251 switch (chip_id & 0xF0000000) {
280 printf(" (SecExtID=%.8x/ChipID=%.8x)\n", sec_id, chip_id);
282 gd->ram_size = dram_init_banksize_int(1);
287 #ifdef CONFIG_EP93XX_SPI
291 * EGIO0-EGIPO7 -> port A
292 * EGIO8-EGIP15 -> port B
295 static void ep93xx_set_epgio(unsigned num)
297 struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
299 writel(readl(®s->padr) | (1<<num), ®s->padr);
301 writel(readl(®s->pbdr) | (1<<(num-8)), ®s->pbdr);
304 static void ep93xx_clear_epgio(unsigned num)
306 struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
308 writel(readl(®s->padr) & (~(1<<num)), ®s->padr);
310 writel(readl(®s->pbdr) & (~(1<<(num-8))), ®s->pbdr);
313 static void ep93xx_dir_epgio_out(unsigned num)
315 struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
317 writel(readl(®s->paddr) | (1<<num), ®s->paddr);
319 writel(readl(®s->pbddr) | (1<<(num-8)), ®s->pbddr);
322 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
324 if (bus == 0 && cs < 16)
330 void spi_cs_activate(struct spi_slave *slave)
332 ep93xx_clear_epgio(slave->cs);
335 void spi_cs_deactivate(struct spi_slave *slave)
337 ep93xx_set_epgio(slave->cs);
340 #ifdef CONFIG_MMC_SPI
343 #ifndef CONFIG_MMC_SPI_CS_EPGIO
344 # define CONFIG_MMC_SPI_CS_EPGIO 4
347 #ifndef CONFIG_MMC_SPI_SPEED
348 # define CONFIG_MMC_SPI_SPEED 25000000
351 #ifndef CONFIG_MMC_SPI_MODE
352 # define CONFIG_MMC_SPI_MODE SPI_MODE_0
355 int board_mmc_init(bd_t *bis)
357 struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
359 ep93xx_set_epgio(CONFIG_MMC_SPI_CS_EPGIO);
360 ep93xx_dir_epgio_out(CONFIG_MMC_SPI_CS_EPGIO);
362 #ifdef CONFIG_MMC_SPI_POWER_EGPIO
363 ep93xx_dir_epgio_out(CONFIG_MMC_SPI_POWER_EGPIO);
364 ep93xx_set_epgio(CONFIG_MMC_SPI_POWER_EGPIO);
365 #elif defined(CONFIG_MMC_SPI_NPOWER_EGPIO)
366 ep93xx_dir_epgio_out(CONFIG_MMC_SPI_NPOWER_EGPIO);
367 ep93xx_clear_epgio(CONFIG_MMC_SPI_NPOWER_EGPIO);
369 struct mmc *mmc = mmc_spi_init(0, CONFIG_MMC_SPI_CS_EPGIO,
370 CONFIG_MMC_SPI_SPEED, CONFIG_MMC_SPI_MODE);
373 printf("Failed to create MMC Device\n");
381 #endif /* CONFIG_MMC_SPI */
382 #endif /* CONFIG_EP93XX_SPI */