2 * (C) Copyright 2003-2007
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * (C) Copyright 2004-2005
9 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/processor.h>
35 #ifdef CONFIG_OF_FLAT_TREE
37 #endif /* CONFIG_OF_FLAT_TREE */
43 * Helper function to initialize SDRAM controller.
45 static void sdram_start(int hi_addr)
47 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
49 /* unlock mode register */
50 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
53 /* precharge all banks */
54 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
58 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
61 /* auto refresh, second time */
62 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
65 /* set mode register */
66 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
68 /* normal operation */
69 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
71 #endif /* CFG_RAMBOOT */
74 * Initalize SDRAM - configure SDRAM controller, detect memory size.
76 long int initdram(int board_type)
82 /* configure SDRAM start/end for detection */
83 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
85 /* setup config registers */
86 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
87 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
90 test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
92 test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
99 /* memory smaller than 1MB is impossible */
100 if (dramsize < (1 << 20))
103 /* set SDRAM CS0 size according to the amount of RAM found */
105 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
106 __builtin_ffs(dramsize >> 20) - 1;
108 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
109 #else /* CFG_RAMBOOT */
110 /* retrieve size of memory connected to SDRAM CS0 */
111 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
112 if (dramsize >= 0x13)
113 dramsize = (1 << (dramsize - 0x13)) << 20;
116 #endif /* CFG_RAMBOOT */
119 * On MPC5200B we need to set the special configuration delay in the
120 * DDR controller. Refer to chapter 8.7.5 SDelay--MBAR + 0x0190 of
121 * the MPC5200B User's Manual.
123 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
124 __asm__ volatile ("sync");
132 puts("Board: CM1.QP1\n");
137 int board_early_init_r(void)
140 * Now, when we are in RAM, enable flash write access for detection
141 * process. Note that CS_BOOT cannot be cleared when executing in
144 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
150 int post_hotkeys_pressed(void)
154 #endif /* CONFIG_POST */
157 #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
158 void post_word_store(ulong a)
160 vu_long *save_addr = (vu_long *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
165 ulong post_word_load(void)
167 vu_long *save_addr = (vu_long *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
170 #endif /* CONFIG_POST || CONFIG_LOGBUFFER */
173 #ifdef CONFIG_MISC_INIT_R
174 int misc_init_r(void)
176 #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
180 /* Read ethaddr from EEPROM */
181 if (i2c_read(CFG_I2C_EEPROM, CONFIG_MAC_OFFSET, 2, buf, 6) == 0) {
182 sprintf(str, "%02X:%02X:%02X:%02X:%02X:%02X",
183 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
184 /* Check if MAC addr is owned by Schindler */
185 if (strstr(str, "00:06:C3") != str) {
186 printf(LOG_PREFIX "Warning - Illegal MAC address (%s)"
187 " in EEPROM.\n", str);
188 printf(LOG_PREFIX "Using MAC from environment\n");
190 printf(LOG_PREFIX "Using MAC (%s) from I2C EEPROM\n",
192 setenv("ethaddr", str);
195 printf(LOG_PREFIX "Warning - Unable to read MAC from I2C"
196 " device at address %02X:%04X\n", CFG_I2C_EEPROM,
198 printf(LOG_PREFIX "Using MAC from environment\n");
201 #endif /* defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) */
203 #endif /* CONFIG_MISC_INIT_R */
206 #ifdef CONFIG_LAST_STAGE_INIT
207 int last_stage_init(void)
209 #ifdef CONFIG_USB_STORAGE
211 #endif /* CONFIG_USB_STORAGE */
214 #endif /* CONFIG_LAST_STAGE_INIT */
217 #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
218 void ft_board_setup(void *blob, bd_t *bd)
220 ft_cpu_setup(blob, bd);
222 #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */