2 * Board functions for Compulab CM-FX6 board
4 * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
6 * Author: Nikita Kiryanov <nikita@compulab.co.il>
8 * SPDX-License-Identifier: GPL-2.0+
14 #include <dwc_ahsata.h>
15 #include <fsl_esdhc.h>
21 #include <fdt_support.h>
24 #include <asm/arch/crm_regs.h>
25 #include <asm/arch/sys_proto.h>
26 #include <asm/arch/iomux.h>
27 #include <asm/arch/mxc_hdmi.h>
28 #include <asm/mach-imx/mxc_i2c.h>
29 #include <asm/mach-imx/sata.h>
30 #include <asm/mach-imx/video.h>
33 #include <dm/platform_data/serial_mxc.h>
34 #include <dm/device-internal.h>
35 #include <jffs2/load_kernel.h>
37 #include "../common/eeprom.h"
38 #include "../common/common.h"
40 DECLARE_GLOBAL_DATA_PTR;
42 #ifdef CONFIG_SPLASH_SCREEN
43 static struct splash_location cm_fx6_splash_locations[] = {
46 .storage = SPLASH_STORAGE_SF,
47 .flags = SPLASH_STORAGE_RAW,
52 .storage = SPLASH_STORAGE_MMC,
53 .flags = SPLASH_STORAGE_FS,
58 .storage = SPLASH_STORAGE_USB,
59 .flags = SPLASH_STORAGE_FS,
64 .storage = SPLASH_STORAGE_SATA,
65 .flags = SPLASH_STORAGE_FS,
70 int splash_screen_prepare(void)
72 return splash_source_load(cm_fx6_splash_locations,
73 ARRAY_SIZE(cm_fx6_splash_locations));
77 #ifdef CONFIG_IMX_HDMI
78 static void cm_fx6_enable_hdmi(struct display_info_t const *dev)
80 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
82 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
83 imx_enable_hdmi_phy();
86 static struct display_info_t preset_hdmi_1024X768 = {
89 .pixfmt = IPU_PIX_FMT_RGB24,
90 .enable = cm_fx6_enable_hdmi,
104 .vmode = FB_VMODE_NONINTERLACED,
108 static void cm_fx6_setup_display(void)
110 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
113 clrbits_le32(&iomuxc_regs->gpr[3], MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
116 int board_video_skip(void)
119 struct display_info_t *preset;
120 char const *panel = env_get("displaytype");
122 if (!panel) /* Also accept panel for backward compatibility */
123 panel = env_get("panel");
128 if (!strcmp(panel, "HDMI"))
129 preset = &preset_hdmi_1024X768;
133 ret = ipuv3_fb_init(&preset->mode, 0, preset->pixfmt);
135 printf("Can't init display %s: %d\n", preset->mode.name, ret);
139 preset->enable(preset);
140 printf("Display: %s (%ux%u)\n", preset->mode.name, preset->mode.xres,
146 static inline void cm_fx6_setup_display(void) {}
147 #endif /* CONFIG_VIDEO_IPUV3 */
149 #ifdef CONFIG_DWC_AHSATA
150 static int cm_fx6_issd_gpios[] = {
151 /* The order of the GPIOs in the array is important! */
156 CM_FX6_SATA_NSTANDBY1,
157 CM_FX6_SATA_NSTANDBY2,
160 static void cm_fx6_sata_power(int on)
164 if (!on) { /* tell the iSSD that the power will be removed */
165 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1);
169 for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
170 gpio_direction_output(cm_fx6_issd_gpios[i], on);
174 if (!on) /* for compatibility lower the power loss interrupt */
175 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
178 static iomux_v3_cfg_t const sata_pads[] = {
180 IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
181 IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
182 IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
183 IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
185 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
186 IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
187 IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
188 IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
189 IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
192 static int cm_fx6_setup_issd(void)
196 SETUP_IOMUX_PADS(sata_pads);
198 for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
199 ret = gpio_request(cm_fx6_issd_gpios[i], "sata");
204 ret = gpio_request(CM_FX6_SATA_PWLOSS_INT, "sata_pwloss_int");
211 #define CM_FX6_SATA_INIT_RETRIES 10
213 # if !CONFIG_IS_ENABLED(AHCI)
214 int sata_initialize(void)
218 /* Make sure this gpio has logical 0 value */
219 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
221 cm_fx6_sata_power(1);
223 for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
226 printf("SATA setup failed: %d\n", err);
232 err = __sata_initialize();
236 /* There is no device on the SATA port */
237 if (sata_port_status(0, 0) == 0)
240 /* There's a device, but link not established. Retry */
249 cm_fx6_sata_power(0);
256 static int cm_fx6_setup_issd(void) { return 0; }
259 #ifdef CONFIG_SYS_I2C_MXC
260 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
261 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
262 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
265 PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
266 PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL),
268 PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
269 PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL),
273 PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
274 PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL),
276 PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
277 PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL),
281 PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
282 PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL),
284 PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
285 PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL),
289 static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads)
293 ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads);
295 printf("Warning: I2C%d setup failed: %d\n", busnum, ret);
300 static int cm_fx6_setup_i2c(void)
304 /* i2c<x>_pads are wierd macro variables; we can't use an array */
305 err = cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads));
308 err = cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads));
311 err = cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads));
318 static int cm_fx6_setup_i2c(void) { return 0; }
321 #ifdef CONFIG_USB_EHCI_MX6
322 #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
323 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
324 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
325 #define MX6_USBNC_BASEADDR 0x2184800
326 #define USBNC_USB_H1_PWR_POL (1 << 9)
328 static int cm_fx6_setup_usb_host(void)
332 err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst");
336 SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL));
337 SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL));
342 static int cm_fx6_setup_usb_otg(void)
345 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
347 err = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr");
349 printf("USB OTG pwr gpio request failed: %d\n", err);
353 SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL));
354 SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID |
355 MUX_PAD_CTRL(WEAK_PULLDOWN));
356 clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK);
357 /* disable ext. charger detect, or it'll affect signal quality at dp. */
358 return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0);
361 int board_usb_phy_mode(int port)
363 return USB_INIT_HOST;
366 int board_ehci_hcd_init(int port)
369 u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4);
371 /* Only 1 host controller in use. port 0 is OTG & needs no attention */
375 /* Set PWR polarity to match power switch's enable polarity */
376 setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL);
377 ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 0);
382 ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 1);
391 int board_ehci_power(int port, int on)
394 return gpio_direction_output(SB_FX6_USB_OTG_PWR, on);
399 static int cm_fx6_setup_usb_otg(void) { return 0; }
400 static int cm_fx6_setup_usb_host(void) { return 0; }
403 #ifdef CONFIG_FEC_MXC
404 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
405 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
407 static int mx6_rgmii_rework(struct phy_device *phydev)
411 /* Ar8031 phy SmartEEE feature cause link status generates glitch,
412 * which cause ethernet link down/up issue, so disable SmartEEE
414 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
415 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
416 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
417 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
419 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
421 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
422 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
423 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
424 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
426 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
429 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
431 /* introduce tx clock delay */
432 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
433 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
435 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
440 int board_phy_config(struct phy_device *phydev)
442 mx6_rgmii_rework(phydev);
444 if (phydev->drv->config)
445 return phydev->drv->config(phydev);
450 static iomux_v3_cfg_t const enet_pads[] = {
451 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
452 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
453 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
454 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
455 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
456 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
457 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
458 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
459 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
460 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
461 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
462 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
463 IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1 | MUX_PAD_CTRL(NO_PAD_CTRL)),
464 IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL)),
465 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)),
466 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
467 MUX_PAD_CTRL(ENET_PAD_CTRL)),
468 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
469 MUX_PAD_CTRL(ENET_PAD_CTRL)),
470 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
471 MUX_PAD_CTRL(ENET_PAD_CTRL)),
474 static int handle_mac_address(char *env_var, uint eeprom_bus)
476 unsigned char enetaddr[6];
479 rc = eth_env_get_enetaddr(env_var, enetaddr);
483 rc = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus);
487 if (!is_valid_ethaddr(enetaddr))
490 return eth_env_set_enetaddr(env_var, enetaddr);
493 #define SB_FX6_I2C_EEPROM_BUS 0
494 #define NO_MAC_ADDR "No MAC address found for %s\n"
495 int board_eth_init(bd_t *bis)
499 if (handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS))
500 printf(NO_MAC_ADDR, "primary NIC");
502 if (handle_mac_address("eth1addr", SB_FX6_I2C_EEPROM_BUS))
503 printf(NO_MAC_ADDR, "secondary NIC");
505 SETUP_IOMUX_PADS(enet_pads);
507 err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst");
509 printf("Etnernet NRST gpio request failed: %d\n", err);
510 gpio_direction_output(CM_FX6_ENET_NRST, 0);
512 gpio_set_value(CM_FX6_ENET_NRST, 1);
514 return cpu_eth_init(bis);
518 #ifdef CONFIG_NAND_MXS
519 static iomux_v3_cfg_t const nand_pads[] = {
520 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
521 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
522 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
523 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
524 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
525 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
526 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
527 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
528 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
529 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
530 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
531 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
532 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
533 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
536 static void cm_fx6_setup_gpmi_nand(void)
538 SETUP_IOMUX_PADS(nand_pads);
539 /* Enable clock roots */
540 enable_usdhc_clk(1, 3);
541 enable_usdhc_clk(1, 4);
543 setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) |
544 MXC_CCM_CS2CDR_ENFC_CLK_PRED(1) |
545 MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
548 static void cm_fx6_setup_gpmi_nand(void) {}
551 #ifdef CONFIG_FSL_ESDHC
552 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
558 static enum mxc_clock usdhc_clk[3] = {
564 int board_mmc_init(bd_t *bis)
568 cm_fx6_set_usdhc_iomux();
569 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
570 usdhc_cfg[i].sdhc_clk = mxc_get_clock(usdhc_clk[i]);
571 usdhc_cfg[i].max_bus_width = 4;
572 fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
573 enable_usdhc_clk(1, i);
580 #ifdef CONFIG_MXC_SPI
581 int cm_fx6_setup_ecspi(void)
583 cm_fx6_set_ecspi_iomux();
584 return gpio_request(CM_FX6_ECSPI_BUS0_CS0, "ecspi_bus0_cs0");
587 int cm_fx6_setup_ecspi(void) { return 0; }
590 #ifdef CONFIG_OF_BOARD_SETUP
591 #define USDHC3_PATH "/soc/aips-bus@02100000/usdhc@02198000/"
593 struct node_info nodes[] = {
595 * Both entries target the same flash chip. The st,m25p compatible
596 * is used in the vendor device trees, while upstream uses (the
597 * documented) jedec,spi-nor compatible.
599 { "st,m25p", MTD_DEV_TYPE_NOR, },
600 { "jedec,spi-nor", MTD_DEV_TYPE_NOR, },
603 int ft_board_setup(void *blob, bd_t *bd)
608 char baseboard_name[16];
611 fdt_shrink_to_minimum(blob, 0); /* Make room for new properties */
614 if (eth_env_get_enetaddr("ethaddr", enetaddr)) {
615 fdt_find_and_setprop(blob,
616 "/soc/aips-bus@02100000/ethernet@02188000",
617 "local-mac-address", enetaddr, 6, 1);
620 if (eth_env_get_enetaddr("eth1addr", enetaddr)) {
621 fdt_find_and_setprop(blob, "/eth@pcie", "local-mac-address",
625 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
627 baseboard_rev = cl_eeprom_get_board_rev(0);
628 err = cl_eeprom_get_product_name((uchar *)baseboard_name, 0);
629 if (err || baseboard_rev == 0)
630 return 0; /* Assume not an early revision SB-FX6m baseboard */
632 if (!strncmp("SB-FX6m", baseboard_name, 7) && baseboard_rev <= 120) {
633 nodeoffset = fdt_path_offset(blob, USDHC3_PATH);
634 fdt_delprop(blob, nodeoffset, "cd-gpios");
635 fdt_find_and_setprop(blob, USDHC3_PATH, "broken-cd",
637 fdt_find_and_setprop(blob, USDHC3_PATH, "keep-power-in-suspend",
649 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
650 cm_fx6_setup_gpmi_nand();
652 ret = cm_fx6_setup_ecspi();
654 printf("Warning: ECSPI setup failed: %d\n", ret);
656 ret = cm_fx6_setup_usb_otg();
658 printf("Warning: USB OTG setup failed: %d\n", ret);
660 ret = cm_fx6_setup_usb_host();
662 printf("Warning: USB host setup failed: %d\n", ret);
665 * cm-fx6 may have iSSD not assembled and in this case it has
666 * bypasses for a (m)SATA socket on the baseboard. The socketed
667 * device is not controlled by those GPIOs. So just print a warning
668 * if the setup fails.
670 ret = cm_fx6_setup_issd();
672 printf("Warning: iSSD setup failed: %d\n", ret);
674 /* Warn on failure but do not abort boot */
675 ret = cm_fx6_setup_i2c();
677 printf("Warning: I2C setup failed: %d\n", ret);
679 cm_fx6_setup_display();
681 /* This should be done in the MMC driver when MX6 has a clock driver */
682 #ifdef CONFIG_FSL_ESDHC
683 if (IS_ENABLED(CONFIG_BLK)) {
686 cm_fx6_set_usdhc_iomux();
687 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++)
688 enable_usdhc_clk(1, i);
697 puts("Board: CM-FX6\n");
701 int misc_init_r(void)
708 int dram_init_banksize(void)
710 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
711 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
713 switch (gd->ram_size) {
714 case 0x10000000: /* DDR_16BIT_256MB */
715 gd->bd->bi_dram[0].size = 0x10000000;
716 gd->bd->bi_dram[1].size = 0;
718 case 0x20000000: /* DDR_32BIT_512MB */
719 gd->bd->bi_dram[0].size = 0x20000000;
720 gd->bd->bi_dram[1].size = 0;
723 if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
724 gd->bd->bi_dram[0].size = 0x20000000;
725 gd->bd->bi_dram[1].size = 0x20000000;
726 } else { /* DDR_64BIT_1GB */
727 gd->bd->bi_dram[0].size = 0x40000000;
728 gd->bd->bi_dram[1].size = 0;
731 case 0x80000000: /* DDR_64BIT_2GB */
732 gd->bd->bi_dram[0].size = 0x40000000;
733 gd->bd->bi_dram[1].size = 0x40000000;
735 case 0xEFF00000: /* DDR_64BIT_4GB */
736 gd->bd->bi_dram[0].size = 0x70000000;
737 gd->bd->bi_dram[1].size = 0x7FF00000;
746 gd->ram_size = imx_ddr_size();
747 switch (gd->ram_size) {
754 gd->ram_size -= 0x100000;
757 printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size);
764 u32 get_board_rev(void)
766 return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS);
769 static struct mxc_serial_platdata cm_fx6_mxc_serial_plat = {
770 .reg = (struct mxc_uart *)UART4_BASE,
773 U_BOOT_DEVICE(cm_fx6_serial) = {
774 .name = "serial_mxc",
775 .platdata = &cm_fx6_mxc_serial_plat,
778 #if CONFIG_IS_ENABLED(AHCI)
779 static int sata_imx_probe(struct udevice *dev)
783 /* Make sure this gpio has logical 0 value */
784 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
786 cm_fx6_sata_power(1);
788 for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
791 printf("SATA setup failed: %d\n", err);
797 err = dwc_ahsata_probe(dev);
801 /* There is no device on the SATA port */
802 if (sata_dm_port_status(0, 0) == 0)
805 /* There's a device, but link not established. Retry */
806 device_remove(dev, DM_REMOVE_NORMAL);
812 static int sata_imx_remove(struct udevice *dev)
814 cm_fx6_sata_power(0);
820 struct ahci_ops sata_imx_ops = {
821 .port_status = dwc_ahsata_port_status,
822 .reset = dwc_ahsata_bus_reset,
823 .scan = dwc_ahsata_scan,
826 static const struct udevice_id sata_imx_ids[] = {
827 { .compatible = "fsl,imx6q-ahci" },
831 U_BOOT_DRIVER(sata_imx) = {
834 .of_match = sata_imx_ids,
835 .ops = &sata_imx_ops,
836 .probe = sata_imx_probe,
837 .remove = sata_imx_remove, /* reset bus to stop it */