git.sur5r.net Git - u-boot/blob - board/compulab/cm_fx6/cm_fx6.c

   1 /*
   2  * Board functions for Compulab CM-FX6 board
   3  *
   4  * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
   5  *
   6  * Author: Nikita Kiryanov <nikita@compulab.co.il>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <dm.h>
  13 #include <fsl_esdhc.h>
  14 #include <miiphy.h>
  15 #include <netdev.h>
  16 #include <errno.h>
  17 #include <usb.h>
  18 #include <fdt_support.h>
  19 #include <sata.h>
  20 #include <splash.h>
  21 #include <asm/arch/crm_regs.h>
  22 #include <asm/arch/sys_proto.h>
  23 #include <asm/arch/iomux.h>
  24 #include <asm/arch/mxc_hdmi.h>
  25 #include <asm/imx-common/mxc_i2c.h>
  26 #include <asm/imx-common/sata.h>
  27 #include <asm/imx-common/video.h>
  28 #include <asm/io.h>
  29 #include <asm/gpio.h>
  30 #include <dm/platform_data/serial_mxc.h>
  31 #include "common.h"
  32 #include "../common/eeprom.h"
  33 #include "../common/common.h"
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 #ifdef CONFIG_SPLASH_SCREEN
  38 static struct splash_location cm_fx6_splash_locations[] = {
  39         {
  40                 .name = "sf",
  41                 .storage = SPLASH_STORAGE_SF,
  42                 .flags = SPLASH_STORAGE_RAW,
  43                 .offset = 0x100000,
  44         },
  45         {
  46                 .name = "mmc_fs",
  47                 .storage = SPLASH_STORAGE_MMC,
  48                 .flags = SPLASH_STORAGE_FS,
  49                 .devpart = "2:1",
  50         },
  51         {
  52                 .name = "usb_fs",
  53                 .storage = SPLASH_STORAGE_USB,
  54                 .flags = SPLASH_STORAGE_FS,
  55                 .devpart = "0:1",
  56         },
  57         {
  58                 .name = "sata_fs",
  59                 .storage = SPLASH_STORAGE_SATA,
  60                 .flags = SPLASH_STORAGE_FS,
  61                 .devpart = "0:1",
  62         },
  63 };
  64
  65 int splash_screen_prepare(void)
  66 {
  67         return splash_source_load(cm_fx6_splash_locations,
  68                                   ARRAY_SIZE(cm_fx6_splash_locations));
  69 }
  70 #endif
  71
  72 #ifdef CONFIG_IMX_HDMI
  73 static void cm_fx6_enable_hdmi(struct display_info_t const *dev)
  74 {
  75         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  76         imx_setup_hdmi();
  77         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
  78         imx_enable_hdmi_phy();
  79 }
  80
  81 static struct display_info_t preset_hdmi_1024X768 = {
  82         .bus    = -1,
  83         .addr   = 0,
  84         .pixfmt = IPU_PIX_FMT_RGB24,
  85         .enable = cm_fx6_enable_hdmi,
  86         .mode   = {
  87                 .name           = "HDMI",
  88                 .refresh        = 60,
  89                 .xres           = 1024,
  90                 .yres           = 768,
  91                 .pixclock       = 40385,
  92                 .left_margin    = 220,
  93                 .right_margin   = 40,
  94                 .upper_margin   = 21,
  95                 .lower_margin   = 7,
  96                 .hsync_len      = 60,
  97                 .vsync_len      = 10,
  98                 .sync           = FB_SYNC_EXT,
  99                 .vmode          = FB_VMODE_NONINTERLACED,
 100         }
 101 };
 102
 103 static void cm_fx6_setup_display(void)
 104 {
 105         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 106
 107         enable_ipu_clock();
 108         clrbits_le32(&iomuxc_regs->gpr[3], MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
 109 }
 110
 111 int board_video_skip(void)
 112 {
 113         int ret;
 114         struct display_info_t *preset;
 115         char const *panel = getenv("displaytype");
 116
 117         if (!panel) /* Also accept panel for backward compatibility */
 118                 panel = getenv("panel");
 119
 120         if (!panel)
 121                 return -ENOENT;
 122
 123         if (!strcmp(panel, "HDMI"))
 124                 preset = &preset_hdmi_1024X768;
 125         else
 126                 return -EINVAL;
 127
 128         ret = ipuv3_fb_init(&preset->mode, 0, preset->pixfmt);
 129         if (ret) {
 130                 printf("Can't init display %s: %d\n", preset->mode.name, ret);
 131                 return ret;
 132         }
 133
 134         preset->enable(preset);
 135         printf("Display: %s (%ux%u)\n", preset->mode.name, preset->mode.xres,
 136                preset->mode.yres);
 137
 138         return 0;
 139 }
 140 #else
 141 static inline void cm_fx6_setup_display(void) {}
 142 #endif /* CONFIG_VIDEO_IPUV3 */
 143
 144 #ifdef CONFIG_DWC_AHSATA
 145 static int cm_fx6_issd_gpios[] = {
 146         /* The order of the GPIOs in the array is important! */
 147         CM_FX6_SATA_LDO_EN,
 148         CM_FX6_SATA_PHY_SLP,
 149         CM_FX6_SATA_NRSTDLY,
 150         CM_FX6_SATA_PWREN,
 151         CM_FX6_SATA_NSTANDBY1,
 152         CM_FX6_SATA_NSTANDBY2,
 153 };
 154
 155 static void cm_fx6_sata_power(int on)
 156 {
 157         int i;
 158
 159         if (!on) { /* tell the iSSD that the power will be removed */
 160                 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1);
 161                 mdelay(10);
 162         }
 163
 164         for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
 165                 gpio_direction_output(cm_fx6_issd_gpios[i], on);
 166                 udelay(100);
 167         }
 168
 169         if (!on) /* for compatibility lower the power loss interrupt */
 170                 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
 171 }
 172
 173 static iomux_v3_cfg_t const sata_pads[] = {
 174         /* SATA PWR */
 175         IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 176         IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 177         IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 178         IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 179         /* SATA CTRL */
 180         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30  | MUX_PAD_CTRL(NO_PAD_CTRL)),
 181         IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 182         IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 183         IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 184         IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 185 };
 186
 187 static int cm_fx6_setup_issd(void)
 188 {
 189         int ret, i;
 190
 191         SETUP_IOMUX_PADS(sata_pads);
 192
 193         for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
 194                 ret = gpio_request(cm_fx6_issd_gpios[i], "sata");
 195                 if (ret)
 196                         return ret;
 197         }
 198
 199         ret = gpio_request(CM_FX6_SATA_PWLOSS_INT, "sata_pwloss_int");
 200         if (ret)
 201                 return ret;
 202
 203         return 0;
 204 }
 205
 206 #define CM_FX6_SATA_INIT_RETRIES        10
 207 int sata_initialize(void)
 208 {
 209         int err, i;
 210
 211         /* Make sure this gpio has logical 0 value */
 212         gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
 213         udelay(100);
 214         cm_fx6_sata_power(1);
 215
 216         for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
 217                 err = setup_sata();
 218                 if (err) {
 219                         printf("SATA setup failed: %d\n", err);
 220                         return err;
 221                 }
 222
 223                 udelay(100);
 224
 225                 err = __sata_initialize();
 226                 if (!err)
 227                         break;
 228
 229                 /* There is no device on the SATA port */
 230                 if (sata_port_status(0, 0) == 0)
 231                         break;
 232
 233                 /* There's a device, but link not established. Retry */
 234         }
 235
 236         return err;
 237 }
 238
 239 int sata_stop(void)
 240 {
 241         __sata_stop();
 242         cm_fx6_sata_power(0);
 243         mdelay(250);
 244
 245         return 0;
 246 }
 247 #else
 248 static int cm_fx6_setup_issd(void) { return 0; }
 249 #endif
 250
 251 #ifdef CONFIG_SYS_I2C_MXC
 252 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
 253                         PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
 254                         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
 255
 256 I2C_PADS(i2c0_pads,
 257          PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
 258          PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 259          IMX_GPIO_NR(3, 21),
 260          PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
 261          PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 262          IMX_GPIO_NR(3, 28));
 263
 264 I2C_PADS(i2c1_pads,
 265          PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
 266          PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 267          IMX_GPIO_NR(4, 12),
 268          PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
 269          PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 270          IMX_GPIO_NR(4, 13));
 271
 272 I2C_PADS(i2c2_pads,
 273          PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
 274          PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 275          IMX_GPIO_NR(1, 3),
 276          PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
 277          PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 278          IMX_GPIO_NR(1, 6));
 279
 280
 281 static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads)
 282 {
 283         int ret;
 284
 285         ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads);
 286         if (ret)
 287                 printf("Warning: I2C%d setup failed: %d\n", busnum, ret);
 288
 289         return ret;
 290 }
 291
 292 static int cm_fx6_setup_i2c(void)
 293 {
 294         int ret = 0, err;
 295
 296         /* i2c<x>_pads are wierd macro variables; we can't use an array */
 297         err = cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads));
 298         if (err)
 299                 ret = err;
 300         err = cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads));
 301         if (err)
 302                 ret = err;
 303         err = cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads));
 304         if (err)
 305                 ret = err;
 306
 307         return ret;
 308 }
 309 #else
 310 static int cm_fx6_setup_i2c(void) { return 0; }
 311 #endif
 312
 313 #ifdef CONFIG_USB_EHCI_MX6
 314 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
 315                         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
 316                         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
 317 #define MX6_USBNC_BASEADDR      0x2184800
 318 #define USBNC_USB_H1_PWR_POL    (1 << 9)
 319
 320 static int cm_fx6_setup_usb_host(void)
 321 {
 322         int err;
 323
 324         err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst");
 325         if (err)
 326                 return err;
 327
 328         SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL));
 329         SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL));
 330
 331         return 0;
 332 }
 333
 334 static int cm_fx6_setup_usb_otg(void)
 335 {
 336         int err;
 337         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 338
 339         err = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr");
 340         if (err) {
 341                 printf("USB OTG pwr gpio request failed: %d\n", err);
 342                 return err;
 343         }
 344
 345         SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL));
 346         SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID |
 347                                                 MUX_PAD_CTRL(WEAK_PULLDOWN));
 348         clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK);
 349         /* disable ext. charger detect, or it'll affect signal quality at dp. */
 350         return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0);
 351 }
 352
 353 int board_usb_phy_mode(int port)
 354 {
 355         return USB_INIT_HOST;
 356 }
 357
 358 int board_ehci_hcd_init(int port)
 359 {
 360         int ret;
 361         u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4);
 362
 363         /* Only 1 host controller in use. port 0 is OTG & needs no attention */
 364         if (port != 1)
 365                 return 0;
 366
 367         /* Set PWR polarity to match power switch's enable polarity */
 368         setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL);
 369         ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 0);
 370         if (ret)
 371                 return ret;
 372
 373         udelay(10);
 374         ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 1);
 375         if (ret)
 376                 return ret;
 377
 378         mdelay(1);
 379
 380         return 0;
 381 }
 382
 383 int board_ehci_power(int port, int on)
 384 {
 385         if (port == 0)
 386                 return gpio_direction_output(SB_FX6_USB_OTG_PWR, on);
 387
 388         return 0;
 389 }
 390 #else
 391 static int cm_fx6_setup_usb_otg(void) { return 0; }
 392 static int cm_fx6_setup_usb_host(void) { return 0; }
 393 #endif
 394
 395 #ifdef CONFIG_FEC_MXC
 396 #define ENET_PAD_CTRL           (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
 397                                  PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 398
 399 static int mx6_rgmii_rework(struct phy_device *phydev)
 400 {
 401         unsigned short val;
 402
 403         /* Ar8031 phy SmartEEE feature cause link status generates glitch,
 404          * which cause ethernet link down/up issue, so disable SmartEEE
 405          */
 406         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
 407         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
 408         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
 409         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 410         val &= ~(0x1 << 8);
 411         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 412
 413         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 414         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 415         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 416         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 417
 418         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 419         val &= 0xffe3;
 420         val |= 0x18;
 421         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 422
 423         /* introduce tx clock delay */
 424         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 425         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 426         val |= 0x0100;
 427         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 428
 429         return 0;
 430 }
 431
 432 int board_phy_config(struct phy_device *phydev)
 433 {
 434         mx6_rgmii_rework(phydev);
 435
 436         if (phydev->drv->config)
 437                 return phydev->drv->config(phydev);
 438
 439         return 0;
 440 }
 441
 442 static iomux_v3_cfg_t const enet_pads[] = {
 443         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 444         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 445         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 446         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 447         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 448         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 449         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 450         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 451         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 452         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 453         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 454         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 455         IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 456         IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 457         IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)),
 458         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK  |
 459                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 460         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
 461                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 462         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
 463                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 464 };
 465
 466 static int handle_mac_address(char *env_var, uint eeprom_bus)
 467 {
 468         unsigned char enetaddr[6];
 469         int rc;
 470
 471         rc = eth_getenv_enetaddr(env_var, enetaddr);
 472         if (rc)
 473                 return 0;
 474
 475         rc = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus);
 476         if (rc)
 477                 return rc;
 478
 479         if (!is_valid_ethaddr(enetaddr))
 480                 return -1;
 481
 482         return eth_setenv_enetaddr(env_var, enetaddr);
 483 }
 484
 485 #define SB_FX6_I2C_EEPROM_BUS   0
 486 #define NO_MAC_ADDR             "No MAC address found for %s\n"
 487 int board_eth_init(bd_t *bis)
 488 {
 489         int err;
 490
 491         if (handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS))
 492                 printf(NO_MAC_ADDR, "primary NIC");
 493
 494         if (handle_mac_address("eth1addr", SB_FX6_I2C_EEPROM_BUS))
 495                 printf(NO_MAC_ADDR, "secondary NIC");
 496
 497         SETUP_IOMUX_PADS(enet_pads);
 498         /* phy reset */
 499         err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst");
 500         if (err)
 501                 printf("Etnernet NRST gpio request failed: %d\n", err);
 502         gpio_direction_output(CM_FX6_ENET_NRST, 0);
 503         udelay(500);
 504         gpio_set_value(CM_FX6_ENET_NRST, 1);
 505         enable_enet_clk(1);
 506         return cpu_eth_init(bis);
 507 }
 508 #endif
 509
 510 #ifdef CONFIG_NAND_MXS
 511 static iomux_v3_cfg_t const nand_pads[] = {
 512         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 513         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 514         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 515         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
 516         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 517         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 518         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 519         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 520         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 521         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 522         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 523         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 524         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 525         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 526 };
 527
 528 static void cm_fx6_setup_gpmi_nand(void)
 529 {
 530         SETUP_IOMUX_PADS(nand_pads);
 531         /* Enable clock roots */
 532         enable_usdhc_clk(1, 3);
 533         enable_usdhc_clk(1, 4);
 534
 535         setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) |
 536                           MXC_CCM_CS2CDR_ENFC_CLK_PRED(1)   |
 537                           MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
 538 }
 539 #else
 540 static void cm_fx6_setup_gpmi_nand(void) {}
 541 #endif
 542
 543 #ifdef CONFIG_FSL_ESDHC
 544 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
 545         {USDHC1_BASE_ADDR},
 546         {USDHC2_BASE_ADDR},
 547         {USDHC3_BASE_ADDR},
 548 };
 549
 550 static enum mxc_clock usdhc_clk[3] = {
 551         MXC_ESDHC_CLK,
 552         MXC_ESDHC2_CLK,
 553         MXC_ESDHC3_CLK,
 554 };
 555
 556 int board_mmc_init(bd_t *bis)
 557 {
 558         int i;
 559
 560         cm_fx6_set_usdhc_iomux();
 561         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 562                 usdhc_cfg[i].sdhc_clk = mxc_get_clock(usdhc_clk[i]);
 563                 usdhc_cfg[i].max_bus_width = 4;
 564                 fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 565                 enable_usdhc_clk(1, i);
 566         }
 567
 568         return 0;
 569 }
 570 #endif
 571
 572 #ifdef CONFIG_MXC_SPI
 573 int cm_fx6_setup_ecspi(void)
 574 {
 575         cm_fx6_set_ecspi_iomux();
 576         return gpio_request(CM_FX6_ECSPI_BUS0_CS0, "ecspi_bus0_cs0");
 577 }
 578 #else
 579 int cm_fx6_setup_ecspi(void) { return 0; }
 580 #endif
 581
 582 #ifdef CONFIG_OF_BOARD_SETUP
 583 #define USDHC3_PATH     "/soc/aips-bus@02100000/usdhc@02198000/"
 584 int ft_board_setup(void *blob, bd_t *bd)
 585 {
 586         u32 baseboard_rev;
 587         int nodeoffset;
 588         uint8_t enetaddr[6];
 589         char baseboard_name[16];
 590         int err;
 591
 592         /* MAC addr */
 593         if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
 594                 fdt_find_and_setprop(blob,
 595                                      "/soc/aips-bus@02100000/ethernet@02188000",
 596                                      "local-mac-address", enetaddr, 6, 1);
 597         }
 598
 599         if (eth_getenv_enetaddr("eth1addr", enetaddr)) {
 600                 fdt_find_and_setprop(blob, "/eth@pcie", "local-mac-address",
 601                                      enetaddr, 6, 1);
 602         }
 603
 604         baseboard_rev = cl_eeprom_get_board_rev(0);
 605         err = cl_eeprom_get_product_name((uchar *)baseboard_name, 0);
 606         if (err || baseboard_rev == 0)
 607                 return 0; /* Assume not an early revision SB-FX6m baseboard */
 608
 609         if (!strncmp("SB-FX6m", baseboard_name, 7) && baseboard_rev <= 120) {
 610                 fdt_shrink_to_minimum(blob); /* Make room for new properties */
 611                 nodeoffset = fdt_path_offset(blob, USDHC3_PATH);
 612                 fdt_delprop(blob, nodeoffset, "cd-gpios");
 613                 fdt_find_and_setprop(blob, USDHC3_PATH, "non-removable",
 614                                      NULL, 0, 1);
 615                 fdt_find_and_setprop(blob, USDHC3_PATH, "keep-power-in-suspend",
 616                                      NULL, 0, 1);
 617         }
 618
 619         return 0;
 620 }
 621 #endif
 622
 623 int board_init(void)
 624 {
 625         int ret;
 626
 627         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 628         cm_fx6_setup_gpmi_nand();
 629
 630         ret = cm_fx6_setup_ecspi();
 631         if (ret)
 632                 printf("Warning: ECSPI setup failed: %d\n", ret);
 633
 634         ret = cm_fx6_setup_usb_otg();
 635         if (ret)
 636                 printf("Warning: USB OTG setup failed: %d\n", ret);
 637
 638         ret = cm_fx6_setup_usb_host();
 639         if (ret)
 640                 printf("Warning: USB host setup failed: %d\n", ret);
 641
 642         /*
 643          * cm-fx6 may have iSSD not assembled and in this case it has
 644          * bypasses for a (m)SATA socket on the baseboard. The socketed
 645          * device is not controlled by those GPIOs. So just print a warning
 646          * if the setup fails.
 647          */
 648         ret = cm_fx6_setup_issd();
 649         if (ret)
 650                 printf("Warning: iSSD setup failed: %d\n", ret);
 651
 652         /* Warn on failure but do not abort boot */
 653         ret = cm_fx6_setup_i2c();
 654         if (ret)
 655                 printf("Warning: I2C setup failed: %d\n", ret);
 656
 657         cm_fx6_setup_display();
 658
 659         return 0;
 660 }
 661
 662 int checkboard(void)
 663 {
 664         puts("Board: CM-FX6\n");
 665         return 0;
 666 }
 667
 668 int misc_init_r(void)
 669 {
 670         cl_print_pcb_info();
 671
 672         return 0;
 673 }
 674
 675 void dram_init_banksize(void)
 676 {
 677         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 678         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 679
 680         switch (gd->ram_size) {
 681         case 0x10000000: /* DDR_16BIT_256MB */
 682                 gd->bd->bi_dram[0].size = 0x10000000;
 683                 gd->bd->bi_dram[1].size = 0;
 684                 break;
 685         case 0x20000000: /* DDR_32BIT_512MB */
 686                 gd->bd->bi_dram[0].size = 0x20000000;
 687                 gd->bd->bi_dram[1].size = 0;
 688                 break;
 689         case 0x40000000:
 690                 if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
 691                         gd->bd->bi_dram[0].size = 0x20000000;
 692                         gd->bd->bi_dram[1].size = 0x20000000;
 693                 } else { /* DDR_64BIT_1GB */
 694                         gd->bd->bi_dram[0].size = 0x40000000;
 695                         gd->bd->bi_dram[1].size = 0;
 696                 }
 697                 break;
 698         case 0x80000000: /* DDR_64BIT_2GB */
 699                 gd->bd->bi_dram[0].size = 0x40000000;
 700                 gd->bd->bi_dram[1].size = 0x40000000;
 701                 break;
 702         case 0xEFF00000: /* DDR_64BIT_4GB */
 703                 gd->bd->bi_dram[0].size = 0x70000000;
 704                 gd->bd->bi_dram[1].size = 0x7FF00000;
 705                 break;
 706         }
 707 }
 708
 709 int dram_init(void)
 710 {
 711         gd->ram_size = imx_ddr_size();
 712         switch (gd->ram_size) {
 713         case 0x10000000:
 714         case 0x20000000:
 715         case 0x40000000:
 716         case 0x80000000:
 717                 break;
 718         case 0xF0000000:
 719                 gd->ram_size -= 0x100000;
 720                 break;
 721         default:
 722                 printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size);
 723                 return -1;
 724         }
 725
 726         return 0;
 727 }
 728
 729 u32 get_board_rev(void)
 730 {
 731         return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS);
 732 }
 733
 734 static struct mxc_serial_platdata cm_fx6_mxc_serial_plat = {
 735         .reg = (struct mxc_uart *)UART4_BASE,
 736 };
 737
 738 U_BOOT_DEVICE(cm_fx6_serial) = {
 739         .name   = "serial_mxc",
 740         .platdata = &cm_fx6_mxc_serial_plat,
 741 };