2 * Copyright (C) 2015 Compulab, Ltd.
4 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/clock.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/arch/mux.h>
15 #include <asm/arch/ddr_defs.h>
16 #include <asm/errno.h>
19 #include <power/pmic.h>
20 #include <power/tps65218.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
27 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
29 const struct dpll_params dpll_mpu = { 800, 24, 1, -1, -1, -1, -1 };
30 const struct dpll_params dpll_core = { 1000, 24, -1, -1, 10, 8, 4 };
31 const struct dpll_params dpll_per = { 960, 24, 5, -1, -1, -1, -1 };
32 const struct dpll_params dpll_ddr = { 400, 23, 1, -1, 1, -1, -1 };
34 const struct ctrl_ioregs ioregs_ddr3 = {
35 .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
36 .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
37 .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
38 .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
39 .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
40 .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
41 .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
42 .emif_sdram_config_ext = 0x0143,
45 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
46 struct emif_regs ddr3_emif_regs = {
47 .sdram_config = 0x638413B2,
48 .ref_ctrl = 0x00000C30,
49 .sdram_tim1 = 0xEAAAD4DB,
50 .sdram_tim2 = 0x266B7FDA,
51 .sdram_tim3 = 0x107F8678,
52 .read_idle_ctrl = 0x00050000,
53 .zq_config = 0x50074BE4,
54 .temp_alert_config = 0x0,
55 .emif_ddr_phy_ctlr_1 = 0x0E004008,
56 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
57 .emif_ddr_ext_phy_ctrl_2 = 0x00000066,
58 .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
59 .emif_ddr_ext_phy_ctrl_4 = 0x000000B9,
60 .emif_ddr_ext_phy_ctrl_5 = 0x000000E6,
61 .emif_rd_wr_exec_thresh = 0x80000405,
62 .emif_prio_class_serv_map = 0x80000001,
63 .emif_connect_id_serv_1_map = 0x80000094,
64 .emif_connect_id_serv_2_map = 0x00000000,
65 .emif_cos_config = 0x000FFFFF
68 const u32 ext_phy_ctrl_const_base_ddr3[] = {
91 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
93 *regs = ext_phy_ctrl_const_base_ddr3;
94 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
97 const struct dpll_params *get_dpll_ddr_params(void)
102 const struct dpll_params *get_dpll_mpu_params(void)
107 const struct dpll_params *get_dpll_core_params(void)
112 const struct dpll_params *get_dpll_per_params(void)
117 static void enable_vtt_regulator(void)
121 writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
122 writel(GPIO_SETDATAOUT(7), AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
123 temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
124 temp = temp & ~(GPIO_OE_ENABLE(7));
125 writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
128 void sdram_init(void)
130 unsigned long ram_size;
132 enable_vtt_regulator();
133 config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);
134 ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
135 if (ram_size == 0x80000000 ||
136 ram_size == 0x40000000 ||
137 ram_size == 0x20000000)
140 ddr3_emif_regs.sdram_config = 0x638453B2;
141 config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);
142 ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
143 if (ram_size == 0x08000000)
150 /* setup board specific PMIC */
151 int power_init_board(void)
155 power_tps65218_init(I2C_PMIC);
156 p = pmic_get("TPS65218_PMIC");
157 if (p && !pmic_probe(p))
158 puts("PMIC: TPS65218\n");
165 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
168 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
169 i2c_probe(TPS65218_CHIP_PM);
174 #ifdef CONFIG_DRIVER_TI_CPSW
176 static void cpsw_control(int enabled)
181 static struct cpsw_slave_data cpsw_slaves[] = {
183 .slave_reg_ofs = 0x208,
184 .sliver_reg_ofs = 0xd80,
186 .phy_if = PHY_INTERFACE_MODE_RGMII,
189 .slave_reg_ofs = 0x308,
190 .sliver_reg_ofs = 0xdc0,
192 .phy_if = PHY_INTERFACE_MODE_RGMII,
196 static struct cpsw_platform_data cpsw_data = {
197 .mdio_base = CPSW_MDIO_BASE,
198 .cpsw_base = CPSW_BASE,
201 .cpdma_reg_ofs = 0x800,
203 .slave_data = cpsw_slaves,
204 .ale_reg_ofs = 0xd00,
206 .host_port_reg_ofs = 0x108,
207 .hw_stats_reg_ofs = 0x900,
208 .bd_ram_ofs = 0x2000,
209 .mac_control = (1 << 5),
210 .control = cpsw_control,
212 .version = CPSW_CTRL_VERSION_2,
215 #define GPIO_PHY1_RST 170
216 #define GPIO_PHY2_RST 168
218 int board_phy_config(struct phy_device *phydev)
222 /* introduce tx clock delay */
223 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
224 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
226 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
228 if (phydev->drv->config)
229 return phydev->drv->config(phydev);
234 static void board_phy_init(void)
237 writel(0x40003, 0x44e10a74); /* Mux pin as clkout2 */
238 writel(0x10006, 0x44df4108); /* Select EXTDEV as clock source */
239 writel(0x4, 0x44df2e60); /* Set EXTDEV as MNbypass */
242 writel(0x2000009, 0x44df2e6c);
243 writel(0x38a, 0x44df2e70);
247 gpio_request(GPIO_PHY1_RST, "phy1_rst");
248 gpio_request(GPIO_PHY2_RST, "phy2_rst");
249 gpio_direction_output(GPIO_PHY1_RST, 0);
250 gpio_direction_output(GPIO_PHY2_RST, 0);
253 gpio_set_value(GPIO_PHY1_RST, 1);
254 gpio_set_value(GPIO_PHY2_RST, 1);
258 int board_eth_init(bd_t *bis)
263 writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
266 rv = cpsw_register(&cpsw_data);
268 printf("Error %d registering CPSW switch\n", rv);