1 // SPDX-License-Identifier: GPL-2.0+
3 * Creative ZEN X-Fi3 board
5 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
7 * Hardware investigation done by:
9 * Amaury Pouly <amaury.pouly@gmail.com>
16 #include <asm/arch/iomux-mx23.h>
17 #include <asm/arch/imx-regs.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/sys_proto.h>
21 DECLARE_GLOBAL_DATA_PTR;
26 int board_early_init_f(void)
28 /* IO0 clock at 480MHz */
29 mxs_set_ioclk(MXC_IOCLK0, 480000);
31 /* SSP0 clock at 96MHz */
32 mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
39 return mxs_dram_init();
43 static int xfi3_mmc_cd(int id)
47 /* The SSP_DETECT is inverted on this board. */
48 return gpio_get_value(MX23_PAD_SSP1_DETECT__GPIO_2_1);
50 /* Phison bridge always present */
57 int board_mmc_init(bd_t *bis)
62 gpio_direction_input(MX23_PAD_SSP1_DETECT__GPIO_2_1);
63 gpio_direction_output(MX23_PAD_GPMI_D07__GPIO_0_7, 0);
64 ret = mxsmmc_initialize(bis, 0, NULL, xfi3_mmc_cd);
68 /* Phison SD-NAND bridge */
69 ret = mxsmmc_initialize(bis, 1, NULL, xfi3_mmc_cd);
75 #ifdef CONFIG_VIDEO_MXS
76 static int mxsfb_write_byte(uint32_t payload, const unsigned int data)
78 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
79 const unsigned int timeout = 0x10000;
81 if (mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
85 writel((1 << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
86 (1 << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET),
87 ®s->hw_lcdif_transfer_count);
89 writel(LCDIF_CTRL_DATA_SELECT | LCDIF_CTRL_RUN,
90 ®s->hw_lcdif_ctrl_clr);
93 writel(LCDIF_CTRL_DATA_SELECT, ®s->hw_lcdif_ctrl_set);
95 writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set);
97 if (mxs_wait_mask_clr(®s->hw_lcdif_lcdif_stat_reg, 1 << 29,
101 writel(payload, ®s->hw_lcdif_data);
102 return mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
106 static void mxsfb_write_register(uint32_t reg, uint32_t data)
108 mxsfb_write_byte(reg, 0);
109 mxsfb_write_byte(data, 1);
112 static const struct {
119 /* Writing 0x30 to reg. 0x03 flips the LCD */
122 /* This can contain 0x111 to rotate the LCD. */
126 { 0x21, 30, 0x0000 },
127 /* Wait 30 mS here */
129 { 0x11, 30, 0x1038 },
130 /* Wait 30 mS here */
153 { 0x59, 30, 0x0a09 },
154 /* Wait 30 mS here */
155 { 0x07, 30, 0x1017 },
156 /* Wait 40 mS here */
165 void mxsfb_system_setup(void)
167 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
170 /* Switch the LCDIF into System-Mode */
171 writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DOTCLK_MODE |
172 LCDIF_CTRL_BYPASS_COUNT, ®s->hw_lcdif_ctrl_clr);
174 /* Restart the SmartLCD controller */
176 writel(1, ®s->hw_lcdif_ctrl1_set);
178 writel(1, ®s->hw_lcdif_ctrl1_clr);
180 writel(1, ®s->hw_lcdif_ctrl1_set);
183 /* Program the SmartLCD controller */
184 writel(LCDIF_CTRL1_RECOVER_ON_UNDERFLOW, ®s->hw_lcdif_ctrl1_set);
186 writel((0x03 << LCDIF_TIMING_CMD_HOLD_OFFSET) |
187 (0x03 << LCDIF_TIMING_CMD_SETUP_OFFSET) |
188 (0x03 << LCDIF_TIMING_DATA_HOLD_OFFSET) |
189 (0x02 << LCDIF_TIMING_DATA_SETUP_OFFSET),
190 ®s->hw_lcdif_timing);
193 * OTM2201A init and configuration sequence.
195 for (i = 0; i < ARRAY_SIZE(lcd_regs); i++) {
196 mxsfb_write_register(lcd_regs[i].reg, lcd_regs[i].val);
197 if (lcd_regs[i].delay)
198 mdelay(lcd_regs[i].delay);
200 /* Turn on Framebuffer Upload Mode */
201 mxsfb_write_byte(0x22, 0);
203 writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DATA_SELECT,
204 ®s->hw_lcdif_ctrl_set);
210 /* Adress of boot parameters */
211 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
213 /* Turn on PWM backlight */
214 gpio_direction_output(MX23_PAD_PWM2__GPIO_1_28, 1);
219 int board_eth_init(bd_t *bis)
221 usb_eth_initialize(bis);