2 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
5 #include <asm/ppc4xx.h>
7 #include <ppc_asm.tmpl>
10 #include <asm/cache.h>
13 #define LI32(reg,val) \
17 #define WDCR_EBC(reg,val) \
19 mtdcr EBC0_CFGADDR,r4;\
24 #define WDCR_SDRAM(reg,val) \
26 mtdcr SDRAM0_CFGADDR,r4;\
29 mtdcr SDRAM0_CFGDATA,r4
31 /******************************************************************************
32 * Function: ext_bus_cntlr_init
34 * Description: Configures EBC Controller and a few basic chip selects.
36 * CS0 is setup to get the Boot Flash out of the addresss range
37 * so that we may setup a stack. CS7 is setup so that we can
38 * access and reset the hardware watchdog.
40 * IMPORTANT: For pass1 this code must run from
41 * cache since you can not reliably change a peripheral banks
42 * timing register (pbxap) while running code from that bank.
43 * For ex., since we are running from ROM on bank 0, we can NOT
44 * execute the code that modifies bank 0 timings from ROM, so
45 * we run it from cache.
47 * Notes: Does NOT use the stack.
48 *****************************************************************************/
51 .globl ext_bus_cntlr_init
52 .type ext_bus_cntlr_init, @function
55 /********************************************************************
56 * Prefetch entire ext_bus_cntrl_init function into the icache.
57 * This is necessary because we are going to change the same CS we
58 * are executing from. Otherwise a CPU lockup may occur.
59 *******************************************************************/
62 mflr r3 /* get address of ..getAddr */
64 /* Calculate number of cache lines for this function */
65 addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
68 icbt r0, r3 /* prefetch cache line for addr in r3*/
69 addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
70 bdnz ..ebcloop /* continue for $CTR cache lines */
72 /********************************************************************
73 * Delay to ensure all accesses to ROM are complete before changing
74 * bank 0 timings. 200usec should be enough.
75 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
76 *******************************************************************/
78 ori r3, r3, 0xA000 /* wait 200us from reset */
81 bdnz ..spinlp /* spin loop */
83 /********************************************************************
85 *******************************************************************/
89 /********************************************************************
90 * Setup CPC0_CR1: Change PCIINT signal to PerWE
91 *******************************************************************/
96 /********************************************************************
97 * Setup External Bus Controller (EBC).
98 *******************************************************************/
99 WDCR_EBC(EBC0_CFG, 0xd84c0000)
100 /********************************************************************
101 * Memory Bank 0 (Intel 28F128J3 Flash) initialization
102 *******************************************************************/
103 /*WDCR_EBC(PB1AP, 0x02869200)*/
104 WDCR_EBC(PB1AP, 0x07869200)
105 WDCR_EBC(PB0CR, 0xfe0bc000)
106 /********************************************************************
107 * Memory Bank 1 (Holtek HT6542B PS/2) initialization
108 *******************************************************************/
109 WDCR_EBC(PB1AP, 0x1f869200)
110 WDCR_EBC(PB1CR, 0xf0818000)
111 /********************************************************************
112 * Memory Bank 2 (Epson S1D13506) initialization
113 *******************************************************************/
114 WDCR_EBC(PB2AP, 0x05860300)
115 WDCR_EBC(PB2CR, 0xf045a000)
116 /********************************************************************
117 * Memory Bank 3 (Philips SJA1000 CAN Controllers) initialization
118 *******************************************************************/
119 WDCR_EBC(PB3AP, 0x0387d200)
120 WDCR_EBC(PB3CR, 0xf021c000)
121 /********************************************************************
122 * Memory Bank 4-7 (Unused) initialization
123 *******************************************************************/
133 /* We are all done */
134 mtlr r0 /* Restore link register */
135 blr /* Return to calling function */
136 .Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
137 /* end ext_bus_cntlr_init() */
139 /******************************************************************************
140 * Function: sdram_init
142 * Description: Configures SDRAM memory banks.
144 * Notes: Does NOT use the stack.
145 *****************************************************************************/
149 .type sdram_init, @function
153 * Disable memory controller to allow
154 * values to be changed.
156 WDCR_SDRAM(SDRAM0_CFG, 0x00000000)
159 * Configure Memory Banks
161 WDCR_SDRAM(SDRAM0_B0CR, 0x00084001)
162 WDCR_SDRAM(SDRAM0_B1CR, 0x00000000)
163 WDCR_SDRAM(SDRAM0_B2CR, 0x00000000)
164 WDCR_SDRAM(SDRAM0_B3CR, 0x00000000)
167 * Set up SDTR1 (SDRAM Timing Register)
169 WDCR_SDRAM(SDRAM0_TR, 0x00854009)
172 * Set RTR (Refresh Timing Register)
174 WDCR_SDRAM(SDRAM0_RTR, 0x10000000)
175 /* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */
177 /********************************************************************
178 * Delay to ensure 200usec have elapsed since reset. Assume worst
179 * case that the core is running 200Mhz:
180 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
181 *******************************************************************/
183 ori r3, r3, 0xA000 /* Wait >200us from reset */
186 bdnz ..spinlp2 /* spin loop */
188 /********************************************************************
189 * Set memory controller options reg, MCOPT1.
190 *******************************************************************/
191 WDCR_SDRAM(SDRAM0_CFG,0x80800000)
194 blr /* Return to calling function */
195 .Lfe1: .size sdram_init,.Lfe1-sdram_init
196 /* end sdram_init() */