2 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
5 #include <asm/ppc4xx.h>
7 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
9 #include <ppc_asm.tmpl>
12 #include <asm/cache.h>
15 #define LI32(reg,val) \
19 #define WDCR_EBC(reg,val) \
21 mtdcr EBC0_CFGADDR,r4;\
26 #define WDCR_SDRAM(reg,val) \
28 mtdcr SDRAM0_CFGADDR,r4;\
31 mtdcr SDRAM0_CFGDATA,r4
33 /******************************************************************************
34 * Function: ext_bus_cntlr_init
36 * Description: Configures EBC Controller and a few basic chip selects.
38 * CS0 is setup to get the Boot Flash out of the addresss range
39 * so that we may setup a stack. CS7 is setup so that we can
40 * access and reset the hardware watchdog.
42 * IMPORTANT: For pass1 this code must run from
43 * cache since you can not reliably change a peripheral banks
44 * timing register (pbxap) while running code from that bank.
45 * For ex., since we are running from ROM on bank 0, we can NOT
46 * execute the code that modifies bank 0 timings from ROM, so
47 * we run it from cache.
49 * Notes: Does NOT use the stack.
50 *****************************************************************************/
53 .globl ext_bus_cntlr_init
54 .type ext_bus_cntlr_init, @function
57 /********************************************************************
58 * Prefetch entire ext_bus_cntrl_init function into the icache.
59 * This is necessary because we are going to change the same CS we
60 * are executing from. Otherwise a CPU lockup may occur.
61 *******************************************************************/
64 mflr r3 /* get address of ..getAddr */
66 /* Calculate number of cache lines for this function */
67 addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
70 icbt r0, r3 /* prefetch cache line for addr in r3*/
71 addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
72 bdnz ..ebcloop /* continue for $CTR cache lines */
74 /********************************************************************
75 * Delay to ensure all accesses to ROM are complete before changing
76 * bank 0 timings. 200usec should be enough.
77 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
78 *******************************************************************/
80 ori r3, r3, 0xA000 /* wait 200us from reset */
83 bdnz ..spinlp /* spin loop */
85 /********************************************************************
87 *******************************************************************/
91 /********************************************************************
92 * Setup CPC0_CR1: Change PCIINT signal to PerWE
93 *******************************************************************/
98 /********************************************************************
99 * Setup External Bus Controller (EBC).
100 *******************************************************************/
101 WDCR_EBC(EBC0_CFG, 0xd84c0000)
102 /********************************************************************
103 * Memory Bank 0 (Intel 28F128J3 Flash) initialization
104 *******************************************************************/
105 /*WDCR_EBC(PB1AP, 0x02869200)*/
106 WDCR_EBC(PB1AP, 0x07869200)
107 WDCR_EBC(PB0CR, 0xfe0bc000)
108 /********************************************************************
109 * Memory Bank 1 (Holtek HT6542B PS/2) initialization
110 *******************************************************************/
111 WDCR_EBC(PB1AP, 0x1f869200)
112 WDCR_EBC(PB1CR, 0xf0818000)
113 /********************************************************************
114 * Memory Bank 2 (Epson S1D13506) initialization
115 *******************************************************************/
116 WDCR_EBC(PB2AP, 0x05860300)
117 WDCR_EBC(PB2CR, 0xf045a000)
118 /********************************************************************
119 * Memory Bank 3 (Philips SJA1000 CAN Controllers) initialization
120 *******************************************************************/
121 WDCR_EBC(PB3AP, 0x0387d200)
122 WDCR_EBC(PB3CR, 0xf021c000)
123 /********************************************************************
124 * Memory Bank 4-7 (Unused) initialization
125 *******************************************************************/
135 /* We are all done */
136 mtlr r0 /* Restore link register */
137 blr /* Return to calling function */
138 .Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
139 /* end ext_bus_cntlr_init() */
141 /******************************************************************************
142 * Function: sdram_init
144 * Description: Configures SDRAM memory banks.
146 * Notes: Does NOT use the stack.
147 *****************************************************************************/
151 .type sdram_init, @function
155 * Disable memory controller to allow
156 * values to be changed.
158 WDCR_SDRAM(SDRAM0_CFG, 0x00000000)
161 * Configure Memory Banks
163 WDCR_SDRAM(SDRAM0_B0CR, 0x00084001)
164 WDCR_SDRAM(SDRAM0_B1CR, 0x00000000)
165 WDCR_SDRAM(SDRAM0_B2CR, 0x00000000)
166 WDCR_SDRAM(SDRAM0_B3CR, 0x00000000)
169 * Set up SDTR1 (SDRAM Timing Register)
171 WDCR_SDRAM(SDRAM0_TR, 0x00854009)
174 * Set RTR (Refresh Timing Register)
176 WDCR_SDRAM(SDRAM0_RTR, 0x10000000)
177 /* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */
179 /********************************************************************
180 * Delay to ensure 200usec have elapsed since reset. Assume worst
181 * case that the core is running 200Mhz:
182 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
183 *******************************************************************/
185 ori r3, r3, 0xA000 /* Wait >200us from reset */
188 bdnz ..spinlp2 /* spin loop */
190 /********************************************************************
191 * Set memory controller options reg, MCOPT1.
192 *******************************************************************/
193 WDCR_SDRAM(SDRAM0_CFG,0x80800000)
196 blr /* Return to calling function */
197 .Lfe1: .size sdram_init,.Lfe1-sdram_init
198 /* end sdram_init() */