3 # Stefan Herbrechtsmeier <stefan@code.herbrechtsmeier.net>
5 # Based on Kirkwood support:
7 # Marvell Semiconductor <www.marvell.com>
8 # Written-by: Prafulla Wadaskar <prafulla@marvell.com>
10 # See file CREDITS for list of people who contributed to this
13 # This program is free software; you can redistribute it and/or
14 # modify it under the terms of the GNU General Public License as
15 # published by the Free Software Foundation; either version 2 of
16 # the License, or (at your option) any later version.
18 # This program is distributed in the hope that it will be useful,
19 # but WITHOUT ANY WARRANTY; without even the implied warranty of
20 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 # GNU General Public License for more details.
23 # You should have received a copy of the GNU General Public License
24 # along with this program; if not, write to the Free Software
25 # Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
28 # Refer docs/README.kwimage for more details about how-to configure
29 # and create kirkwood boot image
32 # Boot Media configurations
37 # SOC registers configuration using bootrom header extension
38 # Maximum KWBIMAGE_MAX_CONFIG configurations allowed
40 # Configure RGMII-0 interface pad voltage to 1.8V
41 DATA 0xFFD100e0 0x1b1b1b9b
43 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
44 DATA 0xFFD01400 0x43000c30 # DDR Configuration register
45 # bit13-0: 0xc30, 3120 DDR2 clks refresh rate
46 # bit23-14: 0 required
47 # bit24: 1, enable exit self refresh mode on DDR access
49 # bit29-26: 0 required
50 # bit31-30: 0b01 required
52 DATA 0xFFD01404 0x39543000 # DDR Controller Control Low
54 # bit4: 0, addr/cmd in smame cycle
55 # bit5: 0, clk is driven during self refresh, we don't care for APX
56 # bit6: 0, use recommended falling edge of clk for addr/cmd
60 # bit14: 0, input buffer always powered up
61 # bit17-15: 0 required
62 # bit18: 1, cpu lock transaction enabled
64 # bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
65 # bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
66 # bit30-28: 3 required
67 # bit31: 0, no additional STARTBURST delay
69 DATA 0xFFD01408 0x22125451 # DDR Timing (Low)
70 # bit3-0: 1, 18 cycle tRAS (tRAS[3-0])
71 # bit7-4: 5, 6 cycle tRCD
72 # bit11-8: 4, 5 cyle tRP
73 # bit15-12: 5, 6 cyle tWR
74 # bit19-16: 2, 3 cyle tWTR
75 # bit20: 1, 18 cycle tRAS (tRAS[4])
76 # bit23-21: 0 required
77 # bit27-24: 2, 3 cycle tRRD
78 # bit31-28: 2, 3 cyle tRTP
80 DATA 0xFFD0140C 0x00000833 # DDR Timing (High)
81 # bit6-0: 0x33, 33 cycle tRFC
82 # bit8-7: 0, 1 cycle tR2R
83 # bit10-9: 0, 1 cyle tR2W
84 # bit12-11: 1, 2 cylce tW2W
85 # bit31-13: 0 required
87 DATA 0xFFD01410 0x0000000c # DDR Address Control
88 # bit1-0: 0, Cs0width=x8
89 # bit3-2: 3, Cs0size=1Gb
90 # bit5-4: 0, Cs1width=nonexistent
91 # bit7-6: 0, Cs1size=nonexistent
92 # bit9-8: 0, Cs2width=nonexistent
93 # bit11-10: 0, Cs2size=nonexistent
94 # bit13-12: 0, Cs3width=nonexistent
95 # bit15-14: 0, Cs3size=nonexistent
96 # bit16: 0, Cs0AddrSel
97 # bit17: 0, Cs1AddrSel
98 # bit18: 0, Cs2AddrSel
99 # bit19: 0, Cs3AddrSel
100 # bit31-20: 0 required
102 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
103 # bit0: 0, OPEn=OpenPage enabled
104 # bit31-1: 0 required
106 DATA 0xFFD01418 0x00000000 # DDR Operation
107 # bit3-0: 0, Cmd=Normal SDRAM Mode
108 # bit31-4: 0 required
110 DATA 0xFFD0141C 0x00000C52 # DDR Mode
111 # bit2-0: 2, Burst Length (2 required)
112 # bit3: 0, Burst Type (0 required)
113 # bit6-4: 5, CAS Latency (CL) 5
114 # bit7: 0, (Test Mode) Normal operation
115 # bit8: 0, (Reset DLL) Normal operation
116 # bit11-9: 0, Write recovery for auto-precharge (3 required ??)
117 # bit12: 0, Fast Active power down exit time (0 required)
118 # bit31-13: 0 required
120 DATA 0xFFD01420 0x00000040 # DDR Extended Mode
121 # bit0: 0, DRAM DLL enabled
122 # bit1: 0, DRAM drive strength normal
123 # bit2: 0, ODT control Rtt[0] (Rtt=2, 150 ohm termination)
125 # bit6: 1, ODT control Rtt[1] (Rtt=2, 150 ohm termination)
127 # bit10: 0, differential DQS enabled
129 # bit12: 0, DRAM output buffer enabled
130 # bit31-13: 0 required
132 DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
133 # bit2-0: 0x7 required
134 # bit3: 1, MBUS Burst Chop disabled
135 # bit6-4: 0x7 required
137 # bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
138 # bit9: 0, no half clock cycle addition to dataout
139 # bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
140 # bit11: 0, 1/4 clock cycle skew disabled for write mesh
141 # bit15-12: 0xf required
142 # bit31-16: 0 required
144 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing
146 # bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
147 # bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
148 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
149 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
150 # bit31-20: 0 required
152 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing
153 # bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
154 # bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
155 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
156 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
157 # bit31-16: 0 required
159 DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
160 DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
161 # bit0: 1, Window enabled
162 # bit1: 0, Write Protect disabled
163 # bit3-2: 0x0, CS0 hit selected
164 # bit23-4: 0xfffff required
165 # bit31-24: 0x0f, Size (i.e. 256MB)
167 DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
168 DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
169 # bit0: 1, Window enabled
170 # bit1: 0, Write Protect disabled
171 # bit3-2: 1, CS1 hit selected
172 # bit23-4: 0xfffff required
173 # bit31-24: 0x0f, Size (i.e. 256MB)
175 DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
176 DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
178 DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
179 # bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM
180 # bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM
181 # bit15-8: 0 required
182 # bit19-16: 0b0011, (write) M_ODT[0] is asserted during write to DRAM CS0 and CS1
183 # bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM
184 # bit31-24: 0 required
186 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
187 # bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register
188 # bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register
191 DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
192 # bit3-0: 0b0011, internal ODT is asserted during read from DRAM bank 0-1
193 # bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-4
194 # bit9-8: 0, Internal ODT assertion is controlled by fiels
195 # bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
196 # bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
197 # bit14: 1, M_STARTBURST_IN ODT enabled
198 # bit15: 1, DDR IO ODT Unit: Drive ODT calibration values
199 # bit20-16: 0, Pad N channel driving strength for ODT
200 # bit25-21: 0, Pad P channel driving strength for ODT
201 # bit31-26: 0 required
203 DATA 0xFFD01480 0x00000001 # DDR Initialization Control
204 # bit0: 1, enable DDR init upon this register write
205 # bit31-1: 0, required
207 # End of Header extension