4 * http://www.dave-tech.it
5 * http://www.wawnet.biz
6 * mailto:info@wawnet.biz
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/processor.h>
32 /* ------------------------------------------------------------------------- */
38 /* fpga configuration data - gzip compressed and generated by bin2c */
39 const unsigned char fpgadata[] =
45 * include common fpga code (for esd boards)
47 #include "../common/fpga.c"
51 int gunzip(void *, int, unsigned char *, int *);
54 int board_early_init_f (void)
56 out32(GPIO0_OR, CFG_NAND0_CE); /* set initial outputs */
57 out32(GPIO0_OR, CFG_NAND1_CE); /* set initial outputs */
60 * IRQ 0-15 405GP internally generated; active high; level sensitive
61 * IRQ 16 405GP internally generated; active low; level sensitive
63 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
64 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
65 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
66 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
67 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
68 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
69 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
71 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
72 mtdcr(uicer, 0x00000000); /* disable all ints */
73 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
74 mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
75 mtdcr(uictr, 0x10000000); /* set int trigger levels */
76 mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
77 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
80 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
83 mtebc (epcr, 0xa8400000); /* ebc always driven */
85 mtebc (epcr, 0x28400000); /* ebc in high-z */
92 /* ------------------------------------------------------------------------- */
94 int misc_init_f (void)
96 return 0; /* dummy implementation */
99 extern flash_info_t flash_info[]; /* info for FLASH chips */
101 int misc_init_r (void)
103 DECLARE_GLOBAL_DATA_PTR;
105 /* adjust flash start and size as well as the offset */
106 gd->bd->bi_flashstart = 0 - flash_info[0].size;
107 gd->bd->bi_flashoffset= flash_info[0].size - CFG_MONITOR_LEN;
109 volatile unsigned short *fpga_mode =
110 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
111 volatile unsigned char *duart0_mcr =
112 (unsigned char *)((ulong)DUART0_BA + 4);
113 volatile unsigned char *duart1_mcr =
114 (unsigned char *)((ulong)DUART1_BA + 4);
117 char * tmp; /* Temporary char pointer */
119 ulong len = sizeof(fpgadata);
123 unsigned long cntrl0Reg;
125 dst = malloc(CFG_FPGA_MAX_SIZE);
126 if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
127 printf ("GUNZIP ERROR - must RESET board to recover\n");
128 do_reset (NULL, 0, 0, NULL);
131 status = fpga_boot(dst, len);
133 printf("\nFPGA: Booting failed ");
135 case ERROR_FPGA_PRG_INIT_LOW:
136 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
138 case ERROR_FPGA_PRG_INIT_HIGH:
139 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
141 case ERROR_FPGA_PRG_DONE:
142 printf("(Timeout: DONE not high after programming FPGA)\n ");
146 /* display infos on fpgaimage */
148 for (i=0; i<4; i++) {
150 printf("FPGA: %s\n", &(dst[index+1]));
155 for (i=20; i>0; i--) {
156 printf("Rebooting in %2d seconds \r",i);
157 for (index=0;index<1000;index++)
161 do_reset(NULL, 0, 0, NULL);
166 /* display infos on fpgaimage */
168 for (i=0; i<4; i++) {
170 printf("%s ", &(dst[index+1]));
178 * Reset FPGA via FPGA_DATA pin
180 SET_FPGA(FPGA_PRG | FPGA_CLK);
181 udelay(1000); /* wait 1ms */
182 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
183 udelay(1000); /* wait 1ms */
189 * Enable power on PS/2 interface
191 *fpga_mode |= CFG_FPGA_CTRL_PS2_RESET;
194 * Enable interrupts in exar duart mcr[3]
204 * Check Board Identity:
207 int checkboard (void)
209 unsigned char str[64];
210 int i = getenv_r ("serial#", str, sizeof(str));
215 puts ("### No HW ID - assuming PPChameleonEVB");
225 /* ------------------------------------------------------------------------- */
227 long int initdram (int board_type)
231 mtdcr(memcfga, mem_mb0cf);
232 val = mfdcr(memcfgd);
234 #if 0 /* test-only */
243 printf("\nmb0cf=%x\n", val); /* test-only */
244 printf("strap=%x\n", mfdcr(strap)); /* test-only */
247 return (4*1024*1024 << ((val & 0x000e0000) >> 17));
250 /* ------------------------------------------------------------------------- */
254 /* TODO: XXX XXX XXX */
255 printf ("test: 16 MB - ok\n");
260 /* ------------------------------------------------------------------------- */
262 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
264 nand_probe(ulong physadr);
271 #if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME) || \
272 (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
273 debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE);
274 totlen += nand_probe (CFG_NAND0_BASE);
275 #endif /* CONFIG_PPCHAMELEON_MODULE_ME, CONFIG_PPCHAMELEON_MODULE_HI */
277 debug ("Probing at 0x%.8x\n", CFG_NAND1_BASE);
278 totlen += nand_probe (CFG_NAND1_BASE);
280 printf ("%4lu MB\n", totlen >>20);