2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
29 /* ------------------------------------------------------------------------- */
35 /* fpga configuration data - gzip compressed and generated by bin2c */
36 const unsigned char fpgadata[] =
42 * include common fpga code (for esd boards)
44 #include "../common/fpga.c"
48 int gunzip(void *, int, unsigned char *, int *);
51 int board_pre_init (void)
53 out32(GPIO0_OR, CFG_NAND0_CE); /* set initial outputs */
54 out32(GPIO0_OR, CFG_NAND1_CE); /* set initial outputs */
57 * IRQ 0-15 405GP internally generated; active high; level sensitive
58 * IRQ 16 405GP internally generated; active low; level sensitive
60 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
61 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
62 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
63 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
64 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
65 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
66 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
68 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
69 mtdcr(uicer, 0x00000000); /* disable all ints */
70 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
71 mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
72 mtdcr(uictr, 0x10000000); /* set int trigger levels */
73 mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
74 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
77 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
80 mtebc (epcr, 0xa8400000); /* ebc always driven */
82 mtebc (epcr, 0x28400000); /* ebc in high-z */
89 /* ------------------------------------------------------------------------- */
91 int misc_init_f (void)
93 return 0; /* dummy implementation */
97 int misc_init_r (void)
100 DECLARE_GLOBAL_DATA_PTR;
102 volatile unsigned short *fpga_mode =
103 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
104 volatile unsigned char *duart0_mcr =
105 (unsigned char *)((ulong)DUART0_BA + 4);
106 volatile unsigned char *duart1_mcr =
107 (unsigned char *)((ulong)DUART1_BA + 4);
110 char * tmp; /* Temporary char pointer */
112 ulong len = sizeof(fpgadata);
116 unsigned long cntrl0Reg;
118 dst = malloc(CFG_FPGA_MAX_SIZE);
119 if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
120 printf ("GUNZIP ERROR - must RESET board to recover\n");
121 do_reset (NULL, 0, 0, NULL);
124 status = fpga_boot(dst, len);
126 printf("\nFPGA: Booting failed ");
128 case ERROR_FPGA_PRG_INIT_LOW:
129 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
131 case ERROR_FPGA_PRG_INIT_HIGH:
132 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
134 case ERROR_FPGA_PRG_DONE:
135 printf("(Timeout: DONE not high after programming FPGA)\n ");
139 /* display infos on fpgaimage */
141 for (i=0; i<4; i++) {
143 printf("FPGA: %s\n", &(dst[index+1]));
148 for (i=20; i>0; i--) {
149 printf("Rebooting in %2d seconds \r",i);
150 for (index=0;index<1000;index++)
154 do_reset(NULL, 0, 0, NULL);
159 /* display infos on fpgaimage */
161 for (i=0; i<4; i++) {
163 printf("%s ", &(dst[index+1]));
171 * Reset FPGA via FPGA_DATA pin
173 SET_FPGA(FPGA_PRG | FPGA_CLK);
174 udelay(1000); /* wait 1ms */
175 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
176 udelay(1000); /* wait 1ms */
182 * Enable power on PS/2 interface
184 *fpga_mode |= CFG_FPGA_CTRL_PS2_RESET;
187 * Enable interrupts in exar duart mcr[3]
199 * Check Board Identity:
202 int checkboard (void)
204 unsigned char str[64];
205 int i = getenv_r ("serial#", str, sizeof(str));
210 puts ("### No HW ID - assuming PPChameleonEVB");
220 /* ------------------------------------------------------------------------- */
222 long int initdram (int board_type)
226 mtdcr(memcfga, mem_mb0cf);
227 val = mfdcr(memcfgd);
229 #if 0 /* test-only */
238 printf("\nmb0cf=%x\n", val); /* test-only */
239 printf("strap=%x\n", mfdcr(strap)); /* test-only */
242 return (4*1024*1024 << ((val & 0x000e0000) >> 17));
245 /* ------------------------------------------------------------------------- */
249 /* TODO: XXX XXX XXX */
250 printf ("test: 16 MB - ok\n");
255 /* ------------------------------------------------------------------------- */
257 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
259 nand_probe(ulong physadr);
266 debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE);
267 totlen = nand_probe (CFG_NAND0_BASE);
269 debug ("Probing at 0x%.8x\n", CFG_NAND1_BASE);
270 totlen += nand_probe (CFG_NAND1_BASE);
272 printf ("%4lu MB\n", totlen >>20);