2 * (C) Copyright 2001-2003
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
4 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/processor.h>
13 /* ------------------------------------------------------------------------- */
16 #define DBG(x...) printf(x)
23 #ifdef CONFIG_SYS_FPGA_PRG
24 # define FPGA_PRG CONFIG_SYS_FPGA_PRG /* FPGA program pin (ppc output)*/
25 # define FPGA_CLK CONFIG_SYS_FPGA_CLK /* FPGA clk pin (ppc output) */
26 # define FPGA_DATA CONFIG_SYS_FPGA_DATA /* FPGA data pin (ppc output) */
27 # define FPGA_DONE CONFIG_SYS_FPGA_DONE /* FPGA done pin (ppc input) */
28 # define FPGA_INIT CONFIG_SYS_FPGA_INIT /* FPGA init pin (ppc input) */
30 # define FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
31 # define FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
32 # define FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
33 # define FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */
34 # define FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */
37 #define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */
38 #define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */
39 #define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */
41 #define SET_FPGA(data) out32(GPIO0_OR, data)
43 #define FPGA_WRITE_1 { \
44 SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
45 SET_FPGA(FPGA_PRG | FPGA_DATA); /* set data to 1 */ \
46 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \
47 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
49 #define FPGA_WRITE_0 { \
50 SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
51 SET_FPGA(FPGA_PRG); /* set data to 0 */ \
52 SET_FPGA(FPGA_PRG | FPGA_CLK); /* set clock to 1 */ \
53 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
56 static int fpga_boot (unsigned char *fpgadata, int size)
61 #ifdef CONFIG_SYS_FPGA_SPARTAN2
68 /* display infos on fpgaimage */
70 for (i = 0; i < 4; i++) {
71 len = fpgadata[index];
72 DBG ("FPGA: %s\n", &(fpgadata[index + 1]));
76 #ifdef CONFIG_SYS_FPGA_SPARTAN2
77 /* search for preamble 0xFFFFFFFF */
79 if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff)
80 && (fpgadata[index + 2] == 0xff)
81 && (fpgadata[index + 3] == 0xff))
82 break; /* preamble found */
87 /* search for preamble 0xFF2X */
88 for (index = 0; index < size - 1; index++) {
89 if ((fpgadata[index] == 0xff)
90 && ((fpgadata[index + 1] & 0xf0) == 0x30))
96 DBG ("FPGA: configdata starts at position 0x%x\n", index);
97 DBG ("FPGA: length of fpga-data %d\n", size - index);
100 * Setup port pins for fpga programming
102 out32 (GPIO0_ODR, 0x00000000); /* no open drain pins */
103 out32 (GPIO0_TCR, in32 (GPIO0_TCR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* setup for output */
104 out32 (GPIO0_OR, in32 (GPIO0_OR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set pins to high */
107 ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
109 ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
112 * Init fpga by asserting and deasserting PROGRAM*
114 SET_FPGA (FPGA_CLK | FPGA_DATA);
116 /* Wait for FPGA init line low */
118 while (in32 (GPIO0_IR) & FPGA_INIT) {
119 udelay (1000); /* wait 1ms */
120 /* Check for timeout - 100us max, so use 3ms */
122 DBG ("FPGA: Booting failed!\n");
123 return ERROR_FPGA_PRG_INIT_LOW;
128 ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
130 ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
132 /* deassert PROGRAM* */
133 SET_FPGA (FPGA_PRG | FPGA_CLK | FPGA_DATA);
135 /* Wait for FPGA end of init period . */
137 while (!(in32 (GPIO0_IR) & FPGA_INIT)) {
138 udelay (1000); /* wait 1ms */
139 /* Check for timeout */
141 DBG ("FPGA: Booting failed!\n");
142 return ERROR_FPGA_PRG_INIT_HIGH;
147 ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
149 ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
151 DBG ("write configuration data into fpga\n");
152 /* write configuration-data into fpga... */
154 #ifdef CONFIG_SYS_FPGA_SPARTAN2
156 * Load uncompressed image into fpga
158 for (i = index; i < size; i++) {
159 for (j = 0; j < 8; j++) {
160 if ((fpgadata[i] & 0x80) == 0x80) {
168 #else /* ! CONFIG_SYS_FPGA_SPARTAN2 */
189 ** Code 1 .. maxOnes : n '1's followed by '0'
190 ** maxOnes + 1 .. maxOnes + 1 : n - 1 '1's no '0'
191 ** maxOnes + 2 .. 254 : n - (maxOnes + 2) '0's followed by '1'
195 for (i = index; i < size; i++) {
197 if ((b >= 1) && (b <= MAX_ONES)) {
198 for (bit = 0; bit < b; bit++) {
202 } else if (b == (MAX_ONES + 1)) {
203 for (bit = 1; bit < b; bit++) {
206 } else if ((b >= (MAX_ONES + 2)) && (b <= 254)) {
207 for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) {
211 } else if (b == 255) {
215 #endif /* CONFIG_SYS_FPGA_SPARTAN2 */
218 ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
220 ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
223 * Check if fpga's DONE signal - correctly booted ?
226 /* Wait for FPGA end of programming period . */
228 while (!(in32 (GPIO0_IR) & FPGA_DONE)) {
229 udelay (1000); /* wait 1ms */
230 /* Check for timeout */
232 DBG ("FPGA: Booting failed!\n");
233 return ERROR_FPGA_PRG_DONE;
237 DBG ("FPGA: Booting successful!\n");