2 * Copyright (C) 2009, Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
4 * Based on board/freescale/mx31ads/lowlevel_init.S
5 * by Guennadi Liakhovetski.
7 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/imx-regs.h>
32 .macro SETUP_RAM cfg, ctl
33 /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */
34 REG 0xB8001010, 0x00000004
38 REG 0xB8001000, 0x92100000
39 REG 0x80000f00, 0x12344321
40 REG 0xB8001000, 0xa2100000
41 REG 0x80000000, 0x12344321
42 REG 0x80000000, 0x12344321
43 REG 0xB8001000, 0xb2100000
49 REG 0x80000000, 0xDEADBEEF
50 REG 0xB8001010, 0x0000000c
53 /* RedBoot: To support 133MHz DDR */
54 .macro init_drive_strength
56 * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
57 * in SW_PAD_CTL registers
61 ldr r1, =IOMUXC_SW_PAD_CTL(0x2b)
63 bic r0, r0, #(1 << 12)
68 bic r0, r0, #(1 << 22)
78 bic r0, r0, #(1 << 22)
83 bic r0, r0, #(1 << 22)
86 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
87 ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */
90 bic r0, r0, #(1 << 22)
91 bic r0, r0, #(1 << 12)
97 .endm /* init_drive_strength */
104 /* Image Processing Unit: */
105 /* Too early to switch display on? */
106 /* Switch on Display Interface */
107 REG IPU_CONF, IPU_CONF_DI_EN
108 /* Clock Control Module: */
109 REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */
113 REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */
114 /* Switch to MCU PLL */
115 REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
122 ldr r1, MPCTL_PARAM_399
126 /* Set UPLL=240MHz, USB=60MHz */
130 ldr r1, UPCTL_PARAM_240
133 /* default CLKO to 1/8 of the ARM core */
138 /* Default: 1, 4, 12, 1 */
139 REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
142 /* Set stackpointer in internal RAM to call get_ram_size */
143 ldr sp, =(IRAM_BASE_ADDR + IRAM_SIZE - 16)
144 stmfd sp!, {r0-r11, ip, lr}
145 mov ip, lr /* save link reg across call */
148 SETUP_RAM ESDCFG0_256MB, ESDCTL0_256MB
155 SETUP_RAM ESDCFG0_128MB, ESDCTL0_128MB
164 ldmfd sp!, {r0-r11, ip, lr}
165 mov lr, ip /* restore link reg */
171 .word (((1 - 1) << 26) + ((52 - 1) << 16) + (7 << 10) + (35 << 0))
173 .word (((2 - 1) << 26) + ((13 - 1) << 16) + (9 << 10) + (3 << 0))
175 .equ ESDCFG0_128MB, \
176 (0 << 21) + /* tXP */ \
177 (1 << 20) + /* tWTR */ \
178 (2 << 18) + /* tRP */ \
179 (1 << 16) + /* tMRD */ \
180 (0 << 15) + /* tWR */ \
181 (5 << 12) + /* tRAS */ \
182 (1 << 10) + /* tRRD */ \
183 (3 << 8) + /* tCAS */ \
184 (2 << 4) + /* tRCD */ \
185 (0x0F << 0) /* tRC */
187 .equ ESDCTL0_128MB, \
188 (1 << 31) + /* enable */ \
189 (0 << 28) + /* mode */ \
190 (0 << 27) + /* supervisor protect */ \
191 (2 << 24) + /* 13 rows */ \
192 (2 << 20) + /* 10 cols */ \
193 (2 << 16) + /* 32 bit */ \
194 (3 << 13) + /* 7.81us (64ms/8192) */ \
195 (0 << 10) + /* power down timer */ \
196 (0 << 8) + /* full page */ \
197 (1 << 7) + /* burst length */ \
198 (0 << 0) /* precharge timer */
200 .equ ESDCFG0_256MB, \
201 (3 << 21) + /* tXP */ \
202 (0 << 20) + /* tWTR */ \
203 (2 << 18) + /* tRP */ \
204 (1 << 16) + /* tMRD */ \
205 (0 << 15) + /* tWR */ \
206 (5 << 12) + /* tRAS */ \
207 (1 << 10) + /* tRRD */ \
208 (3 << 8) + /* tCAS */ \
209 (2 << 4) + /* tRCD */ \
212 .equ ESDCTL0_256MB, \
216 (3 << 24) + /* 14 rows */ \
217 (2 << 20) + /* 10 cols */ \
219 (4 << 13) + /* 3.91us (64ms/16384) */ \