3 * (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/sys_proto.h>
15 #include <power/pmic.h>
18 #include "qong_fpga.h"
22 DECLARE_GLOBAL_DATA_PTR;
26 /* dram_init must store complete ramsize in gd->ram_size */
27 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
32 static void qong_fpga_reset(void)
34 gpio_set_value(QONG_FPGA_RST_PIN, 0);
36 gpio_set_value(QONG_FPGA_RST_PIN, 1);
41 int board_early_init_f(void)
43 #ifdef CONFIG_QONG_FPGA
44 /* CS1: FPGA/Network Controller/GPIO, 16-bit, no DTACK */
45 static const struct mxc_weimcs cs1 = {
46 /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
47 CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 0, 1),
48 /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
49 CSCR_L(2, 0, 0, 4, 0, 0, 5, 0, 0, 0, 0, 1),
50 /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
51 CSCR_A(0, 4, 0, 2, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0)
54 mxc_setup_weimcs(1, &cs1);
56 /* setup pins for FPGA */
57 mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO));
58 mx31_gpio_mux(IOMUX_MODE(0x7e, MUX_CTL_GPIO));
59 mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC | MUX_CTL_IN_GPIO));
60 mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO));
61 mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO));
65 gpio_direction_output(QONG_FPGA_RST_PIN, 0);
67 /* set interrupt pin as input */
68 gpio_direction_input(QONG_FPGA_IRQ_PIN);
70 /* FPGA JTAG Interface */
71 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS6, MUX_CTL_GPIO));
72 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK6, MUX_CTL_GPIO));
73 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CAPTURE, MUX_CTL_GPIO));
74 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_COMPARE, MUX_CTL_GPIO));
75 gpio_direction_output(QONG_FPGA_TCK_PIN, 0);
76 gpio_direction_output(QONG_FPGA_TMS_PIN, 0);
77 gpio_direction_output(QONG_FPGA_TDI_PIN, 0);
78 gpio_direction_input(QONG_FPGA_TDO_PIN);
81 /* setup pins for UART1 */
82 mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
83 mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
84 mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
85 mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
87 /* setup pins for SPI (pmic) */
88 mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
89 mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
90 mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
91 mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
92 mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
94 /* Setup pins for USB2 Host */
95 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_CLK, MUX_CTL_FUNC));
96 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DIR, MUX_CTL_FUNC));
97 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_NXT, MUX_CTL_FUNC));
98 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC));
99 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC));
100 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC));
102 #define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
103 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
105 mx31_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
106 mx31_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
107 mx31_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
108 mx31_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
109 mx31_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
110 mx31_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
111 mx31_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */
112 mx31_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */
113 mx31_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */
114 mx31_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */
115 mx31_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
116 mx31_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
118 mx31_set_gpr(MUX_PGP_UH2, 1);
127 /* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */
128 /* Assumptions: HCLK = 133 MHz, tACC = 130ns */
129 static const struct mxc_weimcs cs0 = {
130 /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
131 CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 21, 0, 0, 6),
132 /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
133 CSCR_L(0, 1, 3, 3, 1, 1, 5, 1, 0, 0, 0, 1),
134 /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
135 CSCR_A(0, 1, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
138 mxc_setup_weimcs(0, &cs0);
140 /* board id for linux */
141 gd->bd->bi_arch_number = MACH_TYPE_QONG;
142 gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
149 int board_late_init(void)
155 ret = pmic_init(I2C_PMIC);
159 p = pmic_get("FSL_PMIC");
162 /* Enable RTC battery */
163 pmic_reg_read(p, REG_POWER_CTL0, &val);
164 pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN);
165 pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
167 #ifdef CONFIG_HW_WATCHDOG
176 printf("Board: DAVE/DENX Qong\n");
180 int misc_init_r(void)
182 #ifdef CONFIG_QONG_FPGA
185 tmp = *(volatile u32*)QONG_FPGA_CTRL_VERSION;
187 printf("version register = %u.%u.%u\n",
188 (tmp & 0xF000) >> 12, (tmp & 0x0F00) >> 8, tmp & 0x00FF);
193 int board_eth_init(bd_t *bis)
195 #if defined(CONFIG_QONG_FPGA) && defined(CONFIG_DNET)
196 return dnet_eth_initialize(0, (void *)CONFIG_DNET_BASE, -1);
202 #if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT)
203 static void board_nand_setup(void)
205 /* CS3: NAND 8-bit */
206 static const struct mxc_weimcs cs3 = {
207 /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
208 CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 1, 15, 0, 0, 0),
209 /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
210 CSCR_L(2, 0, 0, 1, 3, 1, 3, 3, 0, 0, 0, 1),
211 /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
212 CSCR_A(0, 0, 0, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
215 mxc_setup_weimcs(3, &cs3);
217 mx31_set_gpr(MUX_SDCTL_CSD1_SEL, 1);
219 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO));
220 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO));
221 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_RB, MUX_CTL_IN_GPIO));
223 /* Make sure to reset the fpga else you cannot access NAND */
226 /* Enable NAND flash */
227 gpio_set_value(15, 1);
228 gpio_set_value(14, 1);
229 gpio_direction_output(15, 0);
230 gpio_direction_input(16);
231 gpio_direction_input(14);
235 int qong_nand_rdy(void *chip)
238 return gpio_get_value(16);
241 void qong_nand_select_chip(struct mtd_info *mtd, int chip)
244 gpio_set_value(15, 0);
246 gpio_set_value(15, 1);
250 void qong_nand_plat_init(void *chip)
252 struct nand_chip *nand = (struct nand_chip *)chip;
253 nand->chip_delay = 20;
254 nand->select_chip = qong_nand_select_chip;
255 nand->options &= ~NAND_BUSWIDTH_16;