2 * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
4 * Base on code from TI. Original Notices follow:
6 * (C) Copyright 2008, Texas Instruments, Inc. http://www.ti.com/
8 * Modified for DA8xx EVM.
10 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
12 * Parts are shamelessly stolen from various TI sources, original copyright
14 * -----------------------------------------------------------------
16 * Copyright (C) 2004 Texas Instruments.
18 * ----------------------------------------------------------------------------
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
32 * ----------------------------------------------------------------------------
37 #include <asm/arch/hardware.h>
39 #include "../common/misc.h"
41 DECLARE_GLOBAL_DATA_PTR;
43 #define pinmux &davinci_syscfg_regs->pinmux
45 #ifdef CONFIG_SPI_FLASH
46 /* SPI0 pin muxer settings */
47 const struct pinmux_config spi0_pins[] = {
56 /* UART pin muxer settings */
57 const struct pinmux_config uart_pins[] = {
62 /* I2C pin muxer settings */
63 const struct pinmux_config i2c_pins[] = {
70 #ifndef CONFIG_USE_IRQ
72 * Mask all IRQs by clearing the global enable and setting
73 * the enable clear for all the 90 interrupts.
76 writel(0, &davinci_aintc_regs->ger);
78 writel(0, &davinci_aintc_regs->hier);
80 writel(0xffffffff, &davinci_aintc_regs->ecr1);
81 writel(0xffffffff, &davinci_aintc_regs->ecr2);
82 writel(0xffffffff, &davinci_aintc_regs->ecr3);
85 /* arch number of the board */
86 gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA830_EVM;
88 /* address of boot parameters */
89 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
92 * Power on required peripherals
93 * ARM does not have access by default to PSC0 and PSC1
94 * assuming here that the DSP bootloader has set the IOPU
95 * such that PSC access is available to ARM
97 lpsc_on(DAVINCI_LPSC_AEMIF); /* NAND, NOR */
98 lpsc_on(DAVINCI_LPSC_SPI0); /* Serial Flash */
99 lpsc_on(DAVINCI_LPSC_EMAC); /* image download */
100 lpsc_on(DAVINCI_LPSC_UART2); /* console */
101 lpsc_on(DAVINCI_LPSC_GPIO);
103 /* setup the SUSPSRC for ARM to control emulation suspend */
104 writel(readl(&davinci_syscfg_regs->suspsrc) &
105 ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
106 DAVINCI_SYSCFG_SUSPSRC_SPI0 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
107 DAVINCI_SYSCFG_SUSPSRC_UART2),
108 &davinci_syscfg_regs->suspsrc);
110 #ifdef CONFIG_SPI_FLASH
111 if (davinci_configure_pin_mux(spi0_pins, ARRAY_SIZE(spi0_pins)) != 0)
115 if (davinci_configure_pin_mux(uart_pins, ARRAY_SIZE(uart_pins)) != 0)
118 if (davinci_configure_pin_mux(i2c_pins, ARRAY_SIZE(i2c_pins)) != 0)
121 /* enable the console UART */
122 writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
123 DAVINCI_UART_PWREMU_MGMT_UTRST),
124 &davinci_uart2_ctrl_regs->pwremu_mgmt);