2 * Copyright (C) 2009 David Brownell
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/hardware.h>
11 #include <asm/ti-common/davinci_nand.h>
12 #include <asm/arch/davinci_misc.h>
15 #ifdef CONFIG_DAVINCI_MMC
17 #include <asm/arch/sdmmc_defs.h>
20 DECLARE_GLOBAL_DATA_PTR;
23 * With the DM355 EVM, u-boot is *always* a third stage loader,
24 * unless a JTAG debugger handles the first two stages:
26 * - 1st stage is ROM Boot Loader (RBL), which searches for a
27 * second stage loader in one of three places based on SW7:
28 * NAND (with MMC/SD fallback), MMC/SD, or UART.
30 * - 2nd stage is User Boot Loader (UBL), using at most 30KB
31 * of on-chip SRAM, responsible for lowlevel init, and for
32 * loading the third stage loader into DRAM.
34 * - 3rd stage, that's us!
39 gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM355_EVM;
40 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
42 /* We expect the UBL to have handled "lowlevel init", which
43 * involves setting up at least:
45 * + PLL1 (for ARM and peripherals) and PLL2 (for DDR)
46 * + clock divisors for those PLLs
47 * + LPSC_DDR module enabled
48 * + LPSC_TIMER0 module (still) enabled
50 * + DDR init and timings
51 * + AEMIF timings (for NAND and DM9000)
54 * Some of that is repeated here, mostly as a precaution.
57 /* AEMIF: Some "address" lines are available as GPIOs. A3..A13
58 * could be too if we used A12 as a GPIO during NAND chipselect
59 * (and Linux did too), letting us control the LED on A7/GPIO61.
61 REG(PINMUX2) = 0x0c08;
63 /* UART0 may still be in SyncReset if we didn't boot from UART */
64 davinci_enable_uart0();
66 /* EDMA may be in SyncReset too; turn it on, Linux won't (yet) */
67 lpsc_on(DAVINCI_LPSC_TPCC);
68 lpsc_on(DAVINCI_LPSC_TPTC0);
69 lpsc_on(DAVINCI_LPSC_TPTC1);
74 #ifdef CONFIG_DRIVER_DM9000
75 int board_eth_init(bd_t *bis)
77 return dm9000_initialize(bis);
81 #ifdef CONFIG_NAND_DAVINCI
83 static void nand_dm355evm_select_chip(struct mtd_info *mtd, int chip)
85 struct nand_chip *this = mtd->priv;
86 unsigned long wbase = (unsigned long) this->IO_ADDR_W;
87 unsigned long rbase = (unsigned long) this->IO_ADDR_R;
90 __set_bit(14, &wbase);
91 __set_bit(14, &rbase);
93 __clear_bit(14, &wbase);
94 __clear_bit(14, &rbase);
96 this->IO_ADDR_W = (void *)wbase;
97 this->IO_ADDR_R = (void *)rbase;
100 int board_nand_init(struct nand_chip *nand)
102 davinci_nand_init(nand);
103 nand->select_chip = nand_dm355evm_select_chip;
109 #ifdef CONFIG_DAVINCI_MMC
110 static struct davinci_mmc mmc_sd0 = {
111 .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
112 .input_clk = 108000000,
113 .host_caps = MMC_MODE_4BIT,
114 .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
115 .version = MMC_CTLR_VERSION_1,
118 #ifdef CONFIG_DAVINCI_MMC_SD1
119 static struct davinci_mmc mmc_sd1 = {
120 .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD1_BASE,
121 .input_clk = 108000000,
122 .host_caps = MMC_MODE_4BIT,
123 .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
124 .version = MMC_CTLR_VERSION_1,
128 int board_mmc_init(bd_t *bis)
132 /* Add slot-0 to mmc subsystem */
133 err = davinci_mmc_init(bis, &mmc_sd0);
137 #ifdef CONFIG_DAVINCI_MMC_SD1
138 /* Add slot-1 to mmc subsystem */
139 err = davinci_mmc_init(bis, &mmc_sd1);