2 * Copyright (C) 2009 David Brownell
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include <asm/arch/hardware.h>
23 #include <asm/arch/emif_defs.h>
24 #include <asm/arch/nand_defs.h>
25 #include <asm/arch/davinci_misc.h>
28 #ifdef CONFIG_DAVINCI_MMC
30 #include <asm/arch/sdmmc_defs.h>
33 DECLARE_GLOBAL_DATA_PTR;
36 * With the DM355 EVM, u-boot is *always* a third stage loader,
37 * unless a JTAG debugger handles the first two stages:
39 * - 1st stage is ROM Boot Loader (RBL), which searches for a
40 * second stage loader in one of three places based on SW7:
41 * NAND (with MMC/SD fallback), MMC/SD, or UART.
43 * - 2nd stage is User Boot Loader (UBL), using at most 30KB
44 * of on-chip SRAM, responsible for lowlevel init, and for
45 * loading the third stage loader into DRAM.
47 * - 3rd stage, that's us!
52 gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM355_EVM;
53 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
55 /* We expect the UBL to have handled "lowlevel init", which
56 * involves setting up at least:
58 * + PLL1 (for ARM and peripherals) and PLL2 (for DDR)
59 * + clock divisors for those PLLs
60 * + LPSC_DDR module enabled
61 * + LPSC_TIMER0 module (still) enabled
63 * + DDR init and timings
64 * + AEMIF timings (for NAND and DM9000)
67 * Some of that is repeated here, mostly as a precaution.
70 /* AEMIF: Some "address" lines are available as GPIOs. A3..A13
71 * could be too if we used A12 as a GPIO during NAND chipselect
72 * (and Linux did too), letting us control the LED on A7/GPIO61.
74 REG(PINMUX2) = 0x0c08;
76 /* UART0 may still be in SyncReset if we didn't boot from UART */
77 davinci_enable_uart0();
79 /* EDMA may be in SyncReset too; turn it on, Linux won't (yet) */
80 lpsc_on(DAVINCI_LPSC_TPCC);
81 lpsc_on(DAVINCI_LPSC_TPTC0);
82 lpsc_on(DAVINCI_LPSC_TPTC1);
87 #ifdef CONFIG_DRIVER_DM9000
88 int board_eth_init(bd_t *bis)
90 return dm9000_initialize(bis);
94 #ifdef CONFIG_NAND_DAVINCI
96 static void nand_dm355evm_select_chip(struct mtd_info *mtd, int chip)
98 struct nand_chip *this = mtd->priv;
99 unsigned long wbase = (unsigned long) this->IO_ADDR_W;
100 unsigned long rbase = (unsigned long) this->IO_ADDR_R;
103 __set_bit(14, &wbase);
104 __set_bit(14, &rbase);
106 __clear_bit(14, &wbase);
107 __clear_bit(14, &rbase);
109 this->IO_ADDR_W = (void *)wbase;
110 this->IO_ADDR_R = (void *)rbase;
113 int board_nand_init(struct nand_chip *nand)
115 davinci_nand_init(nand);
116 nand->select_chip = nand_dm355evm_select_chip;
122 #ifdef CONFIG_DAVINCI_MMC
123 static struct davinci_mmc mmc_sd0 = {
124 .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
125 .input_clk = 108000000,
126 .host_caps = MMC_MODE_4BIT,
127 .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
128 .version = MMC_CTLR_VERSION_1,
131 #ifdef CONFIG_DAVINCI_MMC_SD1
132 static struct davinci_mmc mmc_sd1 = {
133 .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD1_BASE,
134 .input_clk = 108000000,
135 .host_caps = MMC_MODE_4BIT,
136 .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
137 .version = MMC_CTLR_VERSION_1,
141 int board_mmc_init(bd_t *bis)
145 /* Add slot-0 to mmc subsystem */
146 err = davinci_mmc_init(bis, &mmc_sd0);
150 #ifdef CONFIG_DAVINCI_MMC_SD1
151 /* Add slot-1 to mmc subsystem */
152 err = davinci_mmc_init(bis, &mmc_sd1);