2 * Copyright (C) 2009 Texas Instruments Incorporated
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include <asm/arch/hardware.h>
23 #include <asm/arch/gpio_defs.h>
24 #include <asm/arch/nand_defs.h>
25 #include "../common/misc.h"
29 DECLARE_GLOBAL_DATA_PTR;
33 struct davinci_gpio *gpio01_base =
34 (struct davinci_gpio *)DAVINCI_GPIO_BANK01;
35 struct davinci_gpio *gpio23_base =
36 (struct davinci_gpio *)DAVINCI_GPIO_BANK23;
37 struct davinci_gpio *gpio67_base =
38 (struct davinci_gpio *)DAVINCI_GPIO_BANK67;
40 gd->bd->bi_arch_number = MACH_TYPE_DM355_LEOPARD;
41 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
43 /* GIO 9 & 10 are used for IO */
44 writel((readl(PINMUX3) & 0XF8FFFFFF), PINMUX3);
46 /* Interrupt set GIO 9 */
47 writel((readl(DAVINCI_GPIO_BINTEN) | 0x1), DAVINCI_GPIO_BINTEN);
50 writel((readl(&gpio01_base->dir) | (1 << 9)), &gpio01_base->dir);
52 /* Both edge trigger GIO 9 */
53 writel((readl(&gpio01_base->set_rising) | (1 << 9)),
54 &gpio01_base->set_rising);
55 writel((readl(&gpio01_base->dir) & ~(1 << 5)), &gpio01_base->dir);
58 writel((readl(&gpio01_base->set_data) & ~(1 << 5)),
59 &gpio01_base->set_data);
61 /* set GIO 10 output */
62 writel((readl(&gpio01_base->dir) & ~(1 << 10)), &gpio01_base->dir);
65 writel((readl(&gpio01_base->set_data) | (1 << 10)),
66 &gpio01_base->set_data);
68 /* set GIO 32 output */
69 writel((readl(&gpio23_base->dir) & ~(1 << 0)), &gpio23_base->dir);
72 writel((readl(&gpio23_base->set_data) | (1 << 0)),
73 &gpio23_base->set_data);
75 /* Enable UART1 MUX Lines */
76 writel((readl(PINMUX0) & ~3), PINMUX0);
77 writel((readl(&gpio67_base->dir) & ~(1 << 6)), &gpio67_base->dir);
78 writel((readl(&gpio67_base->set_data) | (1 << 6)),
79 &gpio67_base->set_data);
84 #ifdef CONFIG_DRIVER_DM9000
85 int board_eth_init(bd_t *bis)
87 return dm9000_initialize(bis);
91 #ifdef CONFIG_NAND_DAVINCI
92 int board_nand_init(struct nand_chip *nand)
94 davinci_nand_init(nand);