2 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
4 * Parts are shamelessly stolen from various TI sources, original copyright
6 * -----------------------------------------------------------------
8 * Copyright (C) 2004 Texas Instruments.
10 * ----------------------------------------------------------------------------
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * ----------------------------------------------------------------------------
29 #include <asm/arch/hardware.h>
30 #include <asm/arch/emac_defs.h>
32 #define MACH_TYPE_DAVINCI_EVM 901
34 DECLARE_GLOBAL_DATA_PTR;
36 extern void i2c_init(int speed, int slaveaddr);
37 extern void timer_init(void);
38 extern int eth_hw_init(void);
42 /* Works on Always On power domain only (no PD argument) */
43 void lpsc_on(unsigned int id)
45 dv_reg_p mdstat, mdctl;
47 if (id >= DAVINCI_LPSC_GEM)
48 return; /* Don't work on DSP Power Domain */
50 mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
51 mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
53 while (REG(PSC_PTSTAT) & 0x01) {;}
55 if ((*mdstat & 0x1f) == 0x03)
56 return; /* Already on and enabled */
60 /* Special treatment for some modules as for sprue14 p.7.4.2 */
61 if ( (id == DAVINCI_LPSC_VPSSSLV) ||
62 (id == DAVINCI_LPSC_EMAC) ||
63 (id == DAVINCI_LPSC_EMAC_WRAPPER) ||
64 (id == DAVINCI_LPSC_MDIO) ||
65 (id == DAVINCI_LPSC_USB) ||
66 (id == DAVINCI_LPSC_ATA) ||
67 (id == DAVINCI_LPSC_VLYNQ) ||
68 (id == DAVINCI_LPSC_UHPI) ||
69 (id == DAVINCI_LPSC_DDR_EMIF) ||
70 (id == DAVINCI_LPSC_AEMIF) ||
71 (id == DAVINCI_LPSC_MMC_SD) ||
72 (id == DAVINCI_LPSC_MEMSTICK) ||
73 (id == DAVINCI_LPSC_McBSP) ||
74 (id == DAVINCI_LPSC_GPIO)
78 REG(PSC_PTCMD) = 0x01;
80 while (REG(PSC_PTSTAT) & 0x03) {;}
81 while ((*mdstat & 0x1f) != 0x03) {;} /* Probably an overkill... */
88 if (REG(PSC_PDSTAT1) & 0x1f)
89 return; /* Already on */
91 REG(PSC_GBLCTL) |= 0x01;
92 REG(PSC_PDCTL1) |= 0x01;
93 REG(PSC_PDCTL1) &= ~0x100;
94 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
95 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
96 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
97 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
98 REG(PSC_PTCMD) = 0x02;
100 for (i = 0; i < 100; i++) {
101 if (REG(PSC_EPCPR) & 0x02)
105 REG(PSC_CHP_SHRTSW) = 0x01;
106 REG(PSC_PDCTL1) |= 0x100;
107 REG(PSC_EPCCR) = 0x02;
109 for (i = 0; i < 100; i++) {
110 if (!(REG(PSC_PTSTAT) & 0x02))
114 REG(PSC_GBLCTL) &= ~0x1f;
120 /* arch number of the board */
121 gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_EVM;
123 /* address of boot parameters */
124 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
126 /* Workaround for TMS320DM6446 errata 1.3.22 */
127 REG(PSC_SILVER_BULLET) = 0;
129 /* Power on required peripherals */
130 lpsc_on(DAVINCI_LPSC_EMAC);
131 lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
132 lpsc_on(DAVINCI_LPSC_MDIO);
133 lpsc_on(DAVINCI_LPSC_I2C);
134 lpsc_on(DAVINCI_LPSC_UART0);
135 lpsc_on(DAVINCI_LPSC_TIMER1);
136 lpsc_on(DAVINCI_LPSC_GPIO);
138 /* Powerup the DSP */
141 /* Bringup UART0 out of reset */
142 REG(UART0_PWREMU_MGMT) = 0x0000e003;
144 /* Enable GIO3.3V cells used for EMAC */
145 REG(VDD3P3V_PWDN) = 0;
147 /* Enable UART0 MUX lines */
150 /* Enable EMAC and AEMIF pins */
151 REG(PINMUX0) = 0x80000c1f;
153 /* Enable I2C pin Mux */
154 REG(PINMUX1) |= (1 << 7);
156 /* Set the Bus Priority Register to appropriate value */
164 int misc_init_r (void)
166 u_int8_t tmp[20], buf[10];
170 clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1);
172 printf ("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27 ) / 2);
173 printf ("DDR Clock : %dMHz\n", (clk / 2));
175 /* Set Ethernet MAC address from EEPROM */
176 if (i2c_read(CFG_I2C_EEPROM_ADDR, 0x7f00, CFG_I2C_EEPROM_ADDR_LEN, buf, 6)) {
177 printf("\nEEPROM @ 0x%02x read FAILED!!!\n", CFG_I2C_EEPROM_ADDR);
180 for (i = 0; i < 6; i++)
183 if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) {
184 sprintf((char *)&tmp[0], "%02x:%02x:%02x:%02x:%02x:%02x",
185 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
186 setenv("ethaddr", (char *)&tmp[0]);
190 if (!eth_hw_init()) {
191 printf("ethernet init failed!\n");
193 printf("ETH PHY : %s\n", phy.name);
196 i2c_read (0x39, 0x00, 1, (u_int8_t *)&i, 1);
198 setenv ("videostd", ((i & 0x80) ? "pal" : "ntsc"));
205 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
206 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;