3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de
5 * Based on da850evm.c, original Copyrights follow:
7 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
9 * Based on da830evm.c. Original Copyrights follow:
11 * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
12 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
33 #include <asm/arch/hardware.h>
34 #include <asm/arch/emif_defs.h>
35 #include <asm/arch/emac_defs.h>
37 #include <asm/arch/davinci_misc.h>
38 #include <asm/arch/gpio.h>
40 DECLARE_GLOBAL_DATA_PTR;
42 #define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
44 /* SPI0 pin muxer settings */
45 static const struct pinmux_config spi1_pins[] = {
52 /* UART0 pin muxer settings */
53 static const struct pinmux_config uart_pins[] = {
60 #ifdef CONFIG_DRIVER_TI_EMAC
62 static const struct pinmux_config emac_pins[] = {
75 #ifdef CONFIG_NAND_DAVINCI
76 const struct pinmux_config nand_pins[] = {
77 { pinmux(7), 1, 0}, /* CS2 */
78 { pinmux(7), 0, 1}, /* CS3 in three state*/
79 { pinmux(7), 1, 4 }, /* EMA_WE */
80 { pinmux(7), 1, 5 }, /* EMA_OE */
81 { pinmux(9), 1, 0 }, /* EMA_D[7] */
82 { pinmux(9), 1, 1 }, /* EMA_D[6] */
83 { pinmux(9), 1, 2 }, /* EMA_D[5] */
84 { pinmux(9), 1, 3 }, /* EMA_D[4] */
85 { pinmux(9), 1, 4 }, /* EMA_D[3] */
86 { pinmux(9), 1, 5 }, /* EMA_D[2] */
87 { pinmux(9), 1, 6 }, /* EMA_D[1] */
88 { pinmux(9), 1, 7 }, /* EMA_D[0] */
89 { pinmux(12), 1, 5 }, /* EMA_A[2] */
90 { pinmux(12), 1, 6 }, /* EMA_A[1] */
91 { pinmux(6), 1, 0 } /* EMA_CLK */
95 const struct pinmux_config gpio_pins[] = {
96 { pinmux(13), 8, 0 }, /* GPIO6[15] RESETOUTn on SOM*/
97 { pinmux(13), 8, 5 }, /* GPIO6[10] U0_SW0 on EA20-00101_2*/
98 { pinmux(13), 8, 3 } /* GPIO6[12] U0_SW1 on EA20-00101_2*/
101 static const struct pinmux_resource pinmuxes[] = {
102 #ifdef CONFIG_SPI_FLASH
103 PINMUX_ITEM(spi1_pins),
105 PINMUX_ITEM(uart_pins),
106 #ifdef CONFIG_NAND_DAVINCI
107 PINMUX_ITEM(nand_pins),
111 static const struct lpsc_resource lpsc[] = {
112 { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
113 { DAVINCI_LPSC_SPI1 }, /* Serial Flash */
114 { DAVINCI_LPSC_EMAC }, /* image download */
115 { DAVINCI_LPSC_UART0 }, /* console */
116 { DAVINCI_LPSC_GPIO },
119 int board_early_init_f(void)
121 struct davinci_gpio *gpio6_base =
122 (struct davinci_gpio *)DAVINCI_GPIO_BANK67;
124 /* PinMux for GPIO */
125 if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
128 /* Set the RESETOUTn low */
129 writel((readl(&gpio6_base->set_data) & ~(1 << 15)),
130 &gpio6_base->set_data);
131 writel((readl(&gpio6_base->dir) & ~(1 << 15)), &gpio6_base->dir);
133 /* Set U0_SW0 low for UART0 as console*/
134 writel((readl(&gpio6_base->set_data) & ~(1 << 10)),
135 &gpio6_base->set_data);
136 writel((readl(&gpio6_base->dir) & ~(1 << 10)), &gpio6_base->dir);
138 /* Set U0_SW1 low for UART0 as console*/
139 writel((readl(&gpio6_base->set_data) & ~(1 << 12)),
140 &gpio6_base->set_data);
141 writel((readl(&gpio6_base->dir) & ~(1 << 12)), &gpio6_base->dir);
143 #ifndef CONFIG_USE_IRQ
148 * NAND CS setup - cycle counts based on da850evm NAND timings in the
149 * Linux kernel @ 25MHz EMIFA
151 #ifdef CONFIG_NAND_DAVINCI
152 writel((DAVINCI_ABCR_WSETUP(0) |
153 DAVINCI_ABCR_WSTROBE(1) |
154 DAVINCI_ABCR_WHOLD(0) |
155 DAVINCI_ABCR_RSETUP(0) |
156 DAVINCI_ABCR_RSTROBE(1) |
157 DAVINCI_ABCR_RHOLD(0) |
159 DAVINCI_ABCR_ASIZE_8BIT),
160 &davinci_emif_regs->ab1cr); /* CS2 */
164 * Power on required peripherals
165 * ARM does not have access by default to PSC0 and PSC1
166 * assuming here that the DSP bootloader has set the IOPU
167 * such that PSC access is available to ARM
169 if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
172 /* setup the SUSPSRC for ARM to control emulation suspend */
173 writel(readl(&davinci_syscfg_regs->suspsrc) &
174 ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
175 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
176 DAVINCI_SYSCFG_SUSPSRC_UART0),
177 &davinci_syscfg_regs->suspsrc);
179 /* configure pinmux settings */
180 if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
183 #ifdef CONFIG_DRIVER_TI_EMAC
184 if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
187 davinci_emac_mii_mode_sel(HAS_RMII);
188 #endif /* CONFIG_DRIVER_TI_EMAC */
190 /* enable the console UART */
191 writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
192 DAVINCI_UART_PWREMU_MGMT_UTRST),
193 &davinci_uart0_ctrl_regs->pwremu_mgmt);
200 /* arch number of the board */
201 gd->bd->bi_arch_number = MACH_TYPE_EA20;
203 /* address of boot parameters */
204 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
208 #ifdef CONFIG_DRIVER_TI_EMAC
211 * Initializes on-board ethernet controllers.
213 int board_eth_init(bd_t *bis)
215 if (!davinci_emac_initialize()) {
216 printf("Error: Ethernet init failed!\n");
221 * This board has a RMII PHY. However, the MDC line on the SOM
222 * must not be disabled (there is no MII PHY on the
223 * baseboard) via the GPIO2[6], because this pin
224 * disables at the same time the SPI flash.
229 #endif /* CONFIG_DRIVER_TI_EMAC */