1 /* Memory sub-system initialization code */
5 #include <asm/regdef.h>
6 #include <asm/au1x00.h>
7 #include <asm/mipsregs.h>
9 #define AU1500_SYS_ADDR 0xB1900000
10 #define sys_endian 0x0038
11 #define CP0_Config0 $16
12 #define CPU_SCALE ((CFG_MHZ) / 12) /* CPU clock is a multiple of 12 MHz */
13 #define MEM_1MS ((CFG_MHZ) * 1000)
22 * Step 1) Establish CPU endian mode.
24 * Switch S1.1 Off(bit7 reads 1) is Little Endian
25 * Switch S1.1 On (bit7 reads 0) is Big Endian
27 #ifdef CONFIG_DBAU1550
53 li t0, DB1XX0_BCSR_ADDR
56 beq zero,t1,big_endian
60 /* Change Au1 core to little endian */
61 li t0, AU1500_SYS_ADDR
69 /* Big Endian is default so nothing to do but fall through */
74 * Step 2) Establish Status Register
75 * (set BEV, clear ERL, clear EXL, clear IE)
81 * Step 3) Establish CP0 Config0
88 * Step 4) Disable Watchpoint facilities
94 * Step 5) Disable the performance counters
96 mtc0 zero, CP0_PERFORMANCE
100 * Step 6) Establish EJTAG Debug register
106 * Step 7) Establish Cause
112 /* Establish Wired (and Random) */
116 #ifdef CONFIG_DBAU1550
117 /* No workaround if running from ram */
121 bne t1, t3, noCacheJump
124 /*** From AMD YAMON ***/
126 * Step 8) Initialize the caches
136 bne t2, t3, cacheloop
139 /* Save return address */
142 /* Run from cacheable space now */
146 li t1, ~0x20000000 /* convert to KSEG0 */
148 addi t0, 5*4 /* 5 insns beyond cachehere */
152 /* Restore return address */
156 * Step 9) Initialize the TLB
158 li t0, 0 # index value
159 li t1, 0x00000000 # entryhi value
160 li t2, 32 # 32 entries
163 /* Probe TLB for matching EntryHi */
168 /* Examine Index[P], 1=no matching entry */
172 addiu t1, t1, 1 # increment t1 (asid)
173 beq zero, t3, tlbloop
176 /* Initialize the TLB entry */
178 mtc0 zero, CP0_ENTRYLO0
179 mtc0 zero, CP0_ENTRYLO1
180 mtc0 zero, CP0_PAGEMASK
188 #endif /* CONFIG_DBAU1550 */
190 /* First setup pll:s to make serial work ok */
191 /* We have a 12 MHz crystal */
193 li t1, CPU_SCALE /* CPU clock */
199 /* wait 1mS for clocks to settle */
206 li t1, 0x20 /* 96 MHz */
207 sw t1, 0(t0) /* aux pll */
210 #ifdef CONFIG_DBAU1550
211 /* Static memory controller */
212 /* RCE0 - can not change while fetching, do so from icache */
213 move t2, ra /* Store return address */
219 move ra, t2 /* Move return addess back */
223 /*** /From YAMON ***/
226 #endif /* CONFIG_DBAU1550 */
228 #ifdef CONFIG_DBAU1550
233 /* RCE0 AMD MirrorBit Flash (?) */
241 #else /* CONFIG_DBAU1550 */
246 /* RCE0 AMD 29LV640M MirrorBit Flash */
254 #endif /* CONFIG_DBAU1550 */
256 /* RCE1 CPLD Board Logic */
269 #ifdef CONFIG_DBAU1550
270 /* RCE2 CPLD Board Logic */
296 /* RCE3 PCMCIA 250ns */
311 /* Set peripherals to a known state */
337 li t0, IC0_FALLINGCLR
370 li t0, IC1_FALLINGCLR
390 li t0, SYS_PININPUTEN
412 /* wait 1mS before setup */
418 #ifdef CONFIG_DBAU1550
419 /* SDCS 0,1,2 DDR SDRAM */
447 li t1, 0x9030060a /* Program refresh - disabled */
456 li t0, MEM_SDPRECMD /* Precharge all */
491 li t0, MEM_SDPRECMD /* Precharge all */
495 /* Issue 2 autoref */
506 li t1, 0x9830060a /* Program refresh - enabled */
510 #else /* CONFIG_DBAU1550 */
540 li t1, 0x64000C24 /* Disable */
555 li t1, 0x66000C24 /* Enable */
569 #endif /* CONFIG_DBAU1550 */
570 /* wait 1mS after setup */