2 * (C) Copyright 2006 DENX Software Engineering
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
26 #ifdef CONFIG_NEW_NAND_CODE
29 #include <asm/arch/pxa-regs.h>
31 /* mk@tbd move this to pxa-regs */
32 #define OSCR_CLK_FREQ 3.250 /* MHz */
34 #define CFG_DFC_DEBUG1
35 #define CFG_DFC_DEBUG2
38 # define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
40 # define DFC_DEBUG1(fmt, args...)
44 # define DFC_DEBUG2(fmt, args...) printf(fmt, ##args)
46 # define DFC_DEBUG2(fmt, args...)
49 static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
51 static struct nand_bbt_descr delta_bbt_descr = {
55 .pattern = scan_ff_pattern
58 static struct nand_oobinfo delta_oob = {
59 .useecc = MTD_NANDECC_AUTOPLACE,
61 .eccpos = {2, 3, 4, 5, 6, 7},
62 .oobfree = { {8, 2}, {12, 4} }
67 * not required for Monahans DFC
69 static void delta_hwcontrol(struct mtd_info *mtdinfo, int cmd)
74 /* read device ready pin */
75 static int delta_device_ready(struct mtd_info *mtdinfo)
85 * Write buf to the DFC Controller Data Buffer
87 static void delta_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
89 unsigned long bytes_multi = len & 0xfffffffc;
90 unsigned long rest = len & 0x3;
91 unsigned long *long_buf;
95 for(i=0; i<bytes_multi; i+=4) {
96 long_buf = (unsigned long*) &buf[i];
101 printf("delta_write_buf: ERROR, writing non 4-byte aligned data.\n");
108 * These functions are quite problematic for the DFC. Luckily they are
109 * not used in the current nand code, except for nand_command, which
110 * we've defined our own anyway. The problem is, that we always need
111 * to write 4 bytes to the DFC Data Buffer, but in these functions we
112 * don't know if to buffer the bytes/half words until we've gathered 4
113 * bytes or if to send them straight away.
115 * Solution: Don't use these with Mona's DFC and complain loudly.
117 static void delta_write_word(struct mtd_info *mtd, u16 word)
119 printf("delta_write_word: WARNING, this function does not work with the Monahans DFC!\n");
121 static void delta_write_byte(struct mtd_info *mtd, u_char byte)
123 printf("delta_write_byte: WARNING, this function does not work with the Monahans DFC!\n");
127 * static void delta_read_buf(struct mtd_info *mtd, const u_char *buf, int len)
129 * Shouldn't this be "u_char * const buf" ?
131 static void delta_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
135 /* we have to be carefull not to overflow the buffer if len is
136 * not a multiple of 4 */
137 unsigned long bytes_multi = len & 0xfffffffc;
138 unsigned long rest = len & 0x3;
139 unsigned long *long_buf;
141 /* if there are any, first copy multiple of 4 bytes */
143 for(i=0; i<bytes_multi; i+=4) {
144 long_buf = (unsigned long*) &buf[i];
149 /* ...then the rest */
151 unsigned long rest_data = NDDB;
153 buf[i+j] = (u_char) ((rest_data>>j) & 0xff);
160 * read a word. Not implemented as not used in NAND code.
162 static u16 delta_read_word(struct mtd_info *mtd)
164 printf("delta_write_byte: UNIMPLEMENTED.\n");
167 /* global var, too bad: mk@tbd: move to ->priv pointer */
168 static unsigned long read_buf = 0;
169 static int bytes_read = -1;
171 /* read a byte from NDDB Because we can only read 4 bytes from NDDB at
172 * a time, we buffer the remaining bytes. The buffer is reset when a
173 * new command is sent to the chip.
175 static u_char delta_read_byte(struct mtd_info *mtd)
177 /* struct nand_chip *this = mtd->priv; */
184 byte = (unsigned char) (read_buf>>(8 * bytes_read++));
188 DFC_DEBUG2("delta_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read, byte, read_buf);
192 /* calculate delta between OSCR values start and now */
193 static unsigned long get_delta(unsigned long start)
195 unsigned long cur = OSCR;
197 if(cur < start) /* OSCR overflowed */
198 return (cur + (start^0xffffffff));
200 return (cur - start);
203 /* delay function, this doesn't belong here */
204 static void wait_us(unsigned long us)
206 unsigned long start = OSCR;
209 while (get_delta(start) < us) {
214 static void delta_clear_nddb()
216 NDCR &= ~NDCR_ND_RUN;
217 wait_us(CFG_NAND_OTHER_TO);
220 /* wait_event with timeout */
221 static unsigned long delta_wait_event2(unsigned long event)
223 unsigned long ndsr, timeout, start = OSCR;
227 else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD))
228 timeout = CFG_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ;
230 timeout = CFG_NAND_OTHER_TO * OSCR_CLK_FREQ;
238 if(get_delta(start) > timeout) {
239 DFC_DEBUG1("delta_wait_event: TIMEOUT waiting for event: 0x%x.\n", event);
249 /* poll the NAND Controller Status Register for event */
250 static void delta_wait_event(unsigned long event)
264 /* we don't always wan't to do this */
265 static void delta_new_cmd()
268 unsigned long status;
270 while(retry++ <= CFG_NAND_SENDCMD_RETRY) {
274 /* set NDCR[NDRUN] */
275 if(!(NDCR & NDCR_ND_RUN))
278 status = delta_wait_event2(NDSR_WRCMDREQ);
280 if(status & NDSR_WRCMDREQ)
283 DFC_DEBUG2("delta_new_cmd: FAILED to get WRITECMDREQ, retry: %d.\n", retry);
286 DFC_DEBUG1("delta_new_cmd: giving up after %d retries.\n", retry);
290 if(NDSR & NDSR_WRCMDREQ) {
291 NDSR |= NDSR_WRCMDREQ; /* Ack */
298 /* this function is called after Programm and Erase Operations to
299 * check for success or failure */
300 static int delta_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
302 unsigned long ndsr=0, event=0;
304 /* mk@tbd set appropriate timeouts */
305 /* if (state == FL_ERASING) */
306 /* timeo = CFG_HZ * 400; */
308 /* timeo = CFG_HZ * 20; */
309 if(state == FL_WRITING) {
310 event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
311 } else if(state == FL_ERASING) {
312 event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
315 ndsr = delta_wait_event2(event);
317 if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000))
318 return(0x1); /* Status Read error */
322 /* cmdfunc send commands to the DFC */
323 static void delta_cmdfunc(struct mtd_info *mtd, unsigned command,
324 int column, int page_addr)
326 /* register struct nand_chip *this = mtd->priv; */
327 unsigned long ndcb0=0, ndcb1=0, ndcb2=0, event=0;
328 unsigned long what_the_hack;
330 /* clear the ugly byte read buffer */
334 /* if command is a double byte cmd, we set bit double cmd bit 19 */
335 /* command2 = (command>>8) & 0xFF; */
336 /* ndcb0 = command | ((command2 ? 1 : 0) << 19); *\/ */
341 ndcb0 = (NAND_CMD_READ0 | (4<<16));
342 column >>= 1; /* adjust for 16 bit bus */
343 ndcb1 = (((column>>1) & 0xff) |
344 ((page_addr<<8) & 0xff00) |
345 ((page_addr<<8) & 0xff0000) |
346 ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
349 case NAND_CMD_READID:
351 DFC_DEBUG2("delta_cmdfunc: NAND_CMD_READID.\n");
352 ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16)); /* addr cycles*/
355 case NAND_CMD_PAGEPROG:
356 /* sent as a multicommand in NAND_CMD_SEQIN */
357 DFC_DEBUG2("delta_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.\n");
359 case NAND_CMD_ERASE1:
360 DFC_DEBUG2("delta_cmdfunc: NAND_CMD_ERASE1.\n");
362 ndcb0 = (0xd060 | (1<<25) | (2<<21) | (1<<19) | (3<<16));
363 ndcb1 = (page_addr & 0x00ffffff);
365 case NAND_CMD_ERASE2:
366 DFC_DEBUG2("delta_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.\n");
369 /* send PAGE_PROG command(0x1080) */
371 DFC_DEBUG2("delta_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG.\n");
372 ndcb0 = (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16));
373 column >>= 1; /* adjust for 16 bit bus */
374 ndcb1 = (((column>>1) & 0xff) |
375 ((page_addr<<8) & 0xff00) |
376 ((page_addr<<8) & 0xff0000) |
377 ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
380 /* case NAND_CMD_SEQIN_pointer_operation: */
382 /* /\* This is confusing because the command names are */
383 /* * different compared to the ones in the K9K12Q0C */
384 /* * datasheet. Infact this has nothing to do with */
385 /* * reading, as the but with page programming */
387 /* * Here we send the multibyte commands */
388 /* * cmd1=0x00, cmd2=0x80 (for programming main area) or */
389 /* * cmd1=0x50, cmd2=0x80 (for spare area) */
391 /* * When all data is written to the buffer, the page */
392 /* * program command (0x10) is sent to actually write */
396 /* printf("delta_cmdfunc: NAND_CMD_SEQIN pointer op called.\n"); */
398 /* ndcb0 = (NAND_CMD_SEQIN<<8) | (1<<21) | (1<<19) | (4<<16); */
399 /* if(column >= mtd->oobblock) { */
400 /* /\* OOB area *\/ */
401 /* column -= mtd->oobblock; */
402 /* ndcb0 |= NAND_CMD_READOOB; */
403 /* } else if (column < 256) { */
404 /* /\* First 256 bytes --> READ0 *\/ */
405 /* ndcb0 |= NAND_CMD_READ0; */
407 /* /\* Only for 8 bit devices - not delta!!! *\/ */
409 /* ndcb0 |= NAND_CMD_READ1; */
411 /* event = NDSR_WRDREQ; */
413 case NAND_CMD_STATUS:
414 DFC_DEBUG2("delta_cmdfunc: NAND_CMD_STATUS.\n");
415 /* oh, this is not nice. for some reason the real
416 * status byte is in the second read from the data
417 * buffer. The hack is to read the first byte right
418 * here, so the next read access by the nand code
419 * yields the right one.
422 ndcb0 = NAND_CMD_STATUS | (4<<21);
424 #undef READ_STATUS_BUG
425 #ifdef READ_STATUS_BUG
429 delta_wait_event2(event);
430 what_the_hack = NDDB;
431 if(what_the_hack != 0xffffffff) {
432 DFC_DEBUG2("what the hack.\n");
433 read_buf = what_the_hack;
440 DFC_DEBUG2("delta_cmdfunc: NAND_CMD_RESET.\n");
441 ndcb0 = NAND_CMD_RESET | (5<<21);
442 event = NDSR_CS0_CMDD;
445 printk("delta_cmdfunc: error, unsupported command.\n");
455 delta_wait_event2(event);
460 static void delta_dfc_gpio_init()
462 DFC_DEBUG2("Setting up DFC GPIO's.\n");
464 /* no idea what is done here, see zylonite.c */
467 DF_ALE_WE1 = 0x00000001;
468 DF_ALE_WE2 = 0x00000001;
469 DF_nCS0 = 0x00000001;
470 DF_nCS1 = 0x00000001;
478 DF_IO10 = 0x00000001;
480 DF_IO11 = 0x00000001;
482 DF_IO12 = 0x00000001;
484 DF_IO13 = 0x00000001;
486 DF_IO14 = 0x00000001;
488 DF_IO15 = 0x00000001;
498 * Board-specific NAND initialization. The following members of the
499 * argument are board-specific (per include/linux/mtd/nand_new.h):
500 * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
501 * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
502 * - hwcontrol: hardwarespecific function for accesing control-lines
503 * - dev_ready: hardwarespecific function for accesing device ready/busy line
504 * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
505 * only be provided if a hardware ECC is available
506 * - eccmode: mode of ecc, see defines
507 * - chip_delay: chip dependent delay for transfering data from array to
509 * - options: various chip options. They can partly be set to inform
510 * nand_scan about special functionality. See the defines for further
512 * Members with a "?" were not set in the merged testing-NAND branch,
513 * so they are not set here either.
515 void board_nand_init(struct nand_chip *nand)
517 unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
519 /* set up GPIO Control Registers */
520 delta_dfc_gpio_init();
522 /* turn on the NAND Controller Clock (104 MHz @ D0) */
523 CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
526 /* printf("stupid loop start...\n"); */
528 /* printf("stupid loop end.\n"); */
531 /* NAND Timing Parameters (in ns) */
532 #define NAND_TIMING_tCH 10
533 #define NAND_TIMING_tCS 0
534 #define NAND_TIMING_tWH 20
535 #define NAND_TIMING_tWP 40
537 #define NAND_TIMING_tRH 20
538 #define NAND_TIMING_tRP 40
540 /* #define NAND_TIMING_tRH 25 */
541 /* #define NAND_TIMING_tRP 50 */
543 #define NAND_TIMING_tR 11123
544 /* #define NAND_TIMING_tWHR 110 */
545 #define NAND_TIMING_tWHR 100
546 #define NAND_TIMING_tAR 10
548 /* Maximum values for NAND Interface Timing Registers in DFC clock
550 #define DFC_MAX_tCH 7
551 #define DFC_MAX_tCS 7
552 #define DFC_MAX_tWH 7
553 #define DFC_MAX_tWP 7
554 #define DFC_MAX_tRH 7
555 #define DFC_MAX_tRP 15
556 #define DFC_MAX_tR 65535
557 #define DFC_MAX_tWHR 15
558 #define DFC_MAX_tAR 15
560 #define DFC_CLOCK 104 /* DFC Clock is 104 MHz */
561 #define DFC_CLK_PER_US DFC_CLOCK/1000 /* clock period in ns */
562 #define MIN(x, y) ((x < y) ? x : y)
565 #ifndef CFG_TIMING_TIGHT
566 tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
568 tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
570 tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1),
572 tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1),
574 tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1),
576 tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1),
578 tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1),
580 tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1),
582 tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1),
584 #else /* this is the tight timing */
586 tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)),
588 tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)),
590 tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)),
592 tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US)),
594 tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US)),
596 tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US)),
598 tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) - tCH - 2),
600 tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) - tCH - 2),
602 tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2),
604 #endif /* CFG_TIMING_TIGHT */
607 DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR);
609 /* tRP value is split in the register */
617 NDTR0CS0 = (tCH << 19) |
625 NDTR1CS0 = (tR << 16) |
631 /* If it doesn't work (unlikely) think about:
633 * - chip select don't care
634 * - read id byte count
636 * Intentionally enabled by not setting bits:
639 * - cs don't care, see if we can enable later!
640 * - row address start position (after second cycle)
641 * - pages per block = 32
642 * - ND_RDY : clears command buffer
644 /* NDCR_NCSX | /\* Chip select busy don't care *\/ */
646 NDCR = (NDCR_SPARE_EN | /* use the spare area */
647 NDCR_DWIDTH_C | /* 16bit DFC data bus width */
648 NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */
649 (7 << 16) | /* read id count = 7 ???? mk@tbd */
650 NDCR_ND_ARB_EN | /* enable bus arbiter */
651 NDCR_RDYM | /* flash device ready ir masked */
652 NDCR_CS0_PAGEDM | /* ND_nCSx page done ir masked */
654 NDCR_CS0_CMDDM | /* ND_CSx command done ir masked */
656 NDCR_CS0_BBDM | /* ND_CSx bad block detect ir masked */
658 NDCR_DBERRM | /* double bit error ir masked */
659 NDCR_SBERRM | /* single bit error ir masked */
660 NDCR_WRDREQM | /* write data request ir masked */
661 NDCR_RDDREQM | /* read data request ir masked */
662 NDCR_WRCMDREQM); /* write command request ir masked */
665 /* wait 10 us due to cmd buffer clear reset */
669 nand->hwcontrol = delta_hwcontrol;
670 /* nand->dev_ready = delta_device_ready; */
671 nand->eccmode = NAND_ECC_SOFT;
672 nand->chip_delay = NAND_DELAY_US;
673 nand->options = NAND_BUSWIDTH_16;
674 nand->waitfunc = delta_wait;
675 nand->read_byte = delta_read_byte;
676 nand->write_byte = delta_write_byte;
677 nand->read_word = delta_read_word;
678 nand->write_word = delta_write_word;
679 nand->read_buf = delta_read_buf;
680 nand->write_buf = delta_write_buf;
682 nand->cmdfunc = delta_cmdfunc;
683 nand->autooob = &delta_oob;
684 nand->badblock_pattern = &delta_bbt_descr;
688 #error "U-Boot legacy NAND support not available for delta board."