4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/arch/imx-regs.h>
30 #include <asm/arch/iomux-mx28.h>
31 #include <asm/arch/clock.h>
32 #include <asm/arch/sys_proto.h>
33 #include <linux/mii.h>
38 DECLARE_GLOBAL_DATA_PTR;
43 int board_early_init_f(void)
45 /* IO0 clock at 480MHz */
46 mx28_set_ioclk(MXC_IOCLK0, 480000);
47 /* IO1 clock at 480MHz */
48 mx28_set_ioclk(MXC_IOCLK1, 480000);
50 /* SSP0 clock at 96MHz */
51 mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
52 /* SSP2 clock at 96MHz */
53 mx28_set_sspclk(MXC_SSPCLK2, 96000, 0);
60 /* Adress of boot parameters */
61 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
68 /* dram_init must store complete ramsize in gd->ram_size */
69 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
74 static int m28_mmc_wp(int id)
77 printf("MXS MMC: Invalid card selected (card id = %d)\n", id);
81 return gpio_get_value(MX28_PAD_AUART2_CTS__GPIO_3_10);
84 int board_mmc_init(bd_t *bis)
86 /* Configure WP as output */
87 gpio_direction_input(MX28_PAD_AUART2_CTS__GPIO_3_10);
89 return mxsmmc_initialize(bis, 0, m28_mmc_wp);
95 #define MII_OPMODE_STRAP_OVERRIDE 0x16
96 #define MII_PHY_CTRL1 0x1e
97 #define MII_PHY_CTRL2 0x1f
99 int fecmxc_mii_postcall(int phy)
101 miiphy_write("FEC1", phy, MII_BMCR, 0x9000);
102 miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202);
104 miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8180);
108 int board_eth_init(bd_t *bis)
110 struct mx28_clkctrl_regs *clkctrl_regs =
111 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
112 struct eth_device *dev;
115 ret = cpu_eth_init(bis);
117 clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet,
118 CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN,
119 CLKCTRL_ENET_TIME_SEL_RMII_CLK);
121 ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
123 printf("FEC MXS: Unable to init FEC0\n");
127 ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE);
129 printf("FEC MXS: Unable to init FEC1\n");
133 dev = eth_get_dev_by_name("FEC0");
135 printf("FEC MXS: Unable to get FEC0 device entry\n");
139 ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
141 printf("FEC MXS: Unable to register FEC0 mii postcall\n");
145 dev = eth_get_dev_by_name("FEC1");
147 printf("FEC MXS: Unable to get FEC1 device entry\n");
151 ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
153 printf("FEC MXS: Unable to register FEC1 mii postcall\n");
160 #ifdef CONFIG_M28_FEC_MAC_IN_OCOTP
162 #define MXS_OCOTP_MAX_TIMEOUT 1000000
163 void imx_get_mac_from_fuse(char *mac)
165 struct mx28_ocotp_regs *ocotp_regs =
166 (struct mx28_ocotp_regs *)MXS_OCOTP_BASE;
171 writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
173 if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
174 MXS_OCOTP_MAX_TIMEOUT)) {
175 printf("MXS FEC: Can't get MAC from OCOTP\n");
179 data = readl(&ocotp_regs->hw_ocotp_cust0);
183 mac[2] = (data >> 24) & 0xff;
184 mac[3] = (data >> 16) & 0xff;
185 mac[4] = (data >> 8) & 0xff;
186 mac[5] = data & 0xff;
189 void imx_get_mac_from_fuse(char *mac)