2 * Freescale i.MX28 Boot PMIC init
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/arch/imx-regs.h>
33 void mx28_power_clock2xtal(void)
35 struct mx28_clkctrl_regs *clkctrl_regs =
36 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
38 /* Set XTAL as CPU reference clock */
39 writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
40 &clkctrl_regs->hw_clkctrl_clkseq_set);
43 void mx28_power_clock2pll(void)
45 struct mx28_clkctrl_regs *clkctrl_regs =
46 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
48 writel(CLKCTRL_PLL0CTRL0_POWER,
49 &clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
51 writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
52 &clkctrl_regs->hw_clkctrl_clkseq_clr);
55 void mx28_power_clear_auto_restart(void)
57 struct mx28_rtc_regs *rtc_regs =
58 (struct mx28_rtc_regs *)MXS_RTC_BASE;
60 writel(RTC_CTRL_SFTRST, &rtc_regs->hw_rtc_ctrl_clr);
61 while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST)
64 writel(RTC_CTRL_CLKGATE, &rtc_regs->hw_rtc_ctrl_clr);
65 while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE)
69 * Due to the hardware design bug of mx28 EVK-A
70 * we need to set the AUTO_RESTART bit.
72 if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
75 while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
78 setbits_le32(&rtc_regs->hw_rtc_persistent0,
79 RTC_PERSISTENT0_AUTO_RESTART);
80 writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_set);
81 writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_clr);
82 while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
84 while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_STALE_REGS_MASK)
88 void mx28_power_set_linreg(void)
90 struct mx28_power_regs *power_regs =
91 (struct mx28_power_regs *)MXS_POWER_BASE;
93 /* Set linear regulator 25mV below switching converter */
94 clrsetbits_le32(&power_regs->hw_power_vdddctrl,
95 POWER_VDDDCTRL_LINREG_OFFSET_MASK,
96 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
98 clrsetbits_le32(&power_regs->hw_power_vddactrl,
99 POWER_VDDACTRL_LINREG_OFFSET_MASK,
100 POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
102 clrsetbits_le32(&power_regs->hw_power_vddioctrl,
103 POWER_VDDIOCTRL_LINREG_OFFSET_MASK,
104 POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
107 void mx28_power_setup_5v_detect(void)
109 struct mx28_power_regs *power_regs =
110 (struct mx28_power_regs *)MXS_POWER_BASE;
112 /* Start 5V detection */
113 clrsetbits_le32(&power_regs->hw_power_5vctrl,
114 POWER_5VCTRL_VBUSVALID_TRSH_MASK,
115 POWER_5VCTRL_VBUSVALID_TRSH_4V4 |
116 POWER_5VCTRL_PWRUP_VBUS_CMPS);
119 void mx28_src_power_init(void)
121 struct mx28_power_regs *power_regs =
122 (struct mx28_power_regs *)MXS_POWER_BASE;
124 /* Improve efficieny and reduce transient ripple */
125 writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
126 POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
128 clrsetbits_le32(&power_regs->hw_power_dclimits,
129 POWER_DCLIMITS_POSLIMIT_BUCK_MASK,
130 0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET);
132 setbits_le32(&power_regs->hw_power_battmonitor,
133 POWER_BATTMONITOR_EN_BATADJ);
135 /* Increase the RCSCALE level for quick DCDC response to dynamic load */
136 clrsetbits_le32(&power_regs->hw_power_loopctrl,
137 POWER_LOOPCTRL_EN_RCSCALE_MASK,
138 POWER_LOOPCTRL_RCSCALE_THRESH |
139 POWER_LOOPCTRL_EN_RCSCALE_8X);
141 clrsetbits_le32(&power_regs->hw_power_minpwr,
142 POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
144 /* 5V to battery handoff ... FIXME */
145 setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
147 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
150 void mx28_power_init_4p2_params(void)
152 struct mx28_power_regs *power_regs =
153 (struct mx28_power_regs *)MXS_POWER_BASE;
155 /* Setup 4P2 parameters */
156 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
157 POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
158 POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET));
160 clrsetbits_le32(&power_regs->hw_power_5vctrl,
161 POWER_5VCTRL_HEADROOM_ADJ_MASK,
162 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET);
164 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
165 POWER_DCDC4P2_DROPOUT_CTRL_MASK,
166 POWER_DCDC4P2_DROPOUT_CTRL_100MV |
167 POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL);
169 clrsetbits_le32(&power_regs->hw_power_5vctrl,
170 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
171 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
174 void mx28_enable_4p2_dcdc_input(int xfer)
176 struct mx28_power_regs *power_regs =
177 (struct mx28_power_regs *)MXS_POWER_BASE;
178 uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
179 uint32_t prev_5v_brnout, prev_5v_droop;
181 prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
182 POWER_5VCTRL_PWDN_5VBRNOUT;
183 prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
184 POWER_CTRL_ENIRQ_VDD5V_DROOP;
186 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
187 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
188 &power_regs->hw_power_reset);
190 clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
192 if (xfer && (readl(&power_regs->hw_power_5vctrl) &
193 POWER_5VCTRL_ENABLE_DCDC)) {
198 * Recording orignal values that will be modified temporarlily
199 * to handle a chip bug. See chip errata for CQ ENGR00115837
201 tmp = readl(&power_regs->hw_power_5vctrl);
202 vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK;
203 vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT;
205 pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO;
208 * Disable mechanisms that get erroneously tripped by when setting
209 * the DCDC4P2 EN_DCDC
211 clrbits_le32(&power_regs->hw_power_5vctrl,
212 POWER_5VCTRL_VBUSVALID_5VDETECT |
213 POWER_5VCTRL_VBUSVALID_TRSH_MASK);
215 writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set);
218 setbits_le32(&power_regs->hw_power_5vctrl,
219 POWER_5VCTRL_DCDC_XFER);
221 clrbits_le32(&power_regs->hw_power_5vctrl,
222 POWER_5VCTRL_DCDC_XFER);
224 setbits_le32(&power_regs->hw_power_5vctrl,
225 POWER_5VCTRL_ENABLE_DCDC);
227 setbits_le32(&power_regs->hw_power_dcdc4p2,
228 POWER_DCDC4P2_ENABLE_DCDC);
233 clrsetbits_le32(&power_regs->hw_power_5vctrl,
234 POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
237 writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set);
240 clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
242 while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
243 clrbits_le32(&power_regs->hw_power_ctrl,
244 POWER_CTRL_VBUS_VALID_IRQ);
246 if (prev_5v_brnout) {
247 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
248 &power_regs->hw_power_5vctrl_set);
249 writel(POWER_RESET_UNLOCK_KEY,
250 &power_regs->hw_power_reset);
252 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
253 &power_regs->hw_power_5vctrl_clr);
254 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
255 &power_regs->hw_power_reset);
258 while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
259 clrbits_le32(&power_regs->hw_power_ctrl,
260 POWER_CTRL_VDD5V_DROOP_IRQ);
263 clrbits_le32(&power_regs->hw_power_ctrl,
264 POWER_CTRL_ENIRQ_VDD5V_DROOP);
266 setbits_le32(&power_regs->hw_power_ctrl,
267 POWER_CTRL_ENIRQ_VDD5V_DROOP);
270 void mx28_power_init_4p2_regulator(void)
272 struct mx28_power_regs *power_regs =
273 (struct mx28_power_regs *)MXS_POWER_BASE;
276 setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
278 writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
280 writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
281 &power_regs->hw_power_5vctrl_clr);
282 clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK);
284 /* Power up the 4p2 rail and logic/control */
285 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
286 &power_regs->hw_power_5vctrl_clr);
289 * Start charging up the 4p2 capacitor. We ramp of this charge
290 * gradually to avoid large inrush current from the 5V cable which can
291 * cause transients/problems
293 mx28_enable_4p2_dcdc_input(0);
295 if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
297 * If we arrived here, we were unable to recover from mx23 chip
298 * errata 5837. 4P2 is disabled and sufficient battery power is
299 * not present. Exiting to not enable DCDC power during 5V
302 clrbits_le32(&power_regs->hw_power_dcdc4p2,
303 POWER_DCDC4P2_ENABLE_DCDC);
304 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
305 &power_regs->hw_power_5vctrl_set);
310 * Here we set the 4p2 brownout level to something very close to 4.2V.
311 * We then check the brownout status. If the brownout status is false,
312 * the voltage is already close to the target voltage of 4.2V so we
313 * can go ahead and set the 4P2 current limit to our max target limit.
314 * If the brownout status is true, we need to ramp us the current limit
315 * so that we don't cause large inrush current issues. We step up the
316 * current limit until the brownout status is false or until we've
317 * reached our maximum defined 4p2 current limit.
319 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
320 POWER_DCDC4P2_BO_MASK,
321 22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
323 if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
324 setbits_le32(&power_regs->hw_power_5vctrl,
325 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
327 tmp = (readl(&power_regs->hw_power_5vctrl) &
328 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
329 POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
331 if (!(readl(&power_regs->hw_power_sts) &
332 POWER_STS_DCDC_4P2_BO)) {
333 tmp = readl(&power_regs->hw_power_5vctrl);
334 tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
336 writel(tmp, &power_regs->hw_power_5vctrl);
340 tmp2 = readl(&power_regs->hw_power_5vctrl);
341 tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
343 POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
344 writel(tmp2, &power_regs->hw_power_5vctrl);
350 clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
351 writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
354 void mx28_power_init_dcdc_4p2_source(void)
356 struct mx28_power_regs *power_regs =
357 (struct mx28_power_regs *)MXS_POWER_BASE;
359 if (!(readl(&power_regs->hw_power_dcdc4p2) &
360 POWER_DCDC4P2_ENABLE_DCDC)) {
364 mx28_enable_4p2_dcdc_input(1);
366 if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
367 clrbits_le32(&power_regs->hw_power_dcdc4p2,
368 POWER_DCDC4P2_ENABLE_DCDC);
369 writel(POWER_5VCTRL_ENABLE_DCDC,
370 &power_regs->hw_power_5vctrl_clr);
371 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
372 &power_regs->hw_power_5vctrl_set);
376 void mx28_power_enable_4p2(void)
378 struct mx28_power_regs *power_regs =
379 (struct mx28_power_regs *)MXS_POWER_BASE;
380 uint32_t vdddctrl, vddactrl, vddioctrl;
383 vdddctrl = readl(&power_regs->hw_power_vdddctrl);
384 vddactrl = readl(&power_regs->hw_power_vddactrl);
385 vddioctrl = readl(&power_regs->hw_power_vddioctrl);
387 setbits_le32(&power_regs->hw_power_vdddctrl,
388 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
389 POWER_VDDDCTRL_PWDN_BRNOUT);
391 setbits_le32(&power_regs->hw_power_vddactrl,
392 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
393 POWER_VDDACTRL_PWDN_BRNOUT);
395 setbits_le32(&power_regs->hw_power_vddioctrl,
396 POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
398 mx28_power_init_4p2_params();
399 mx28_power_init_4p2_regulator();
401 /* Shutdown battery (none present) */
402 clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
403 writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
404 writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
406 mx28_power_init_dcdc_4p2_source();
408 writel(vdddctrl, &power_regs->hw_power_vdddctrl);
410 writel(vddactrl, &power_regs->hw_power_vddactrl);
412 writel(vddioctrl, &power_regs->hw_power_vddioctrl);
415 * Check if FET is enabled on either powerout and if so,
419 tmp |= !(readl(&power_regs->hw_power_vdddctrl) &
420 POWER_VDDDCTRL_DISABLE_FET);
421 tmp |= !(readl(&power_regs->hw_power_vddactrl) &
422 POWER_VDDACTRL_DISABLE_FET);
423 tmp |= !(readl(&power_regs->hw_power_vddioctrl) &
424 POWER_VDDIOCTRL_DISABLE_FET);
426 writel(POWER_CHARGE_ENABLE_LOAD,
427 &power_regs->hw_power_charge_clr);
430 void mx28_boot_valid_5v(void)
432 struct mx28_power_regs *power_regs =
433 (struct mx28_power_regs *)MXS_POWER_BASE;
436 * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
437 * disconnect event. FIXME
439 writel(POWER_5VCTRL_VBUSVALID_5VDETECT,
440 &power_regs->hw_power_5vctrl_set);
442 /* Configure polarity to check for 5V disconnection. */
443 writel(POWER_CTRL_POLARITY_VBUSVALID |
444 POWER_CTRL_POLARITY_VDD5V_GT_VDDIO,
445 &power_regs->hw_power_ctrl_clr);
447 writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
448 &power_regs->hw_power_ctrl_clr);
450 mx28_power_enable_4p2();
453 void mx28_powerdown(void)
455 struct mx28_power_regs *power_regs =
456 (struct mx28_power_regs *)MXS_POWER_BASE;
457 writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
458 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
459 &power_regs->hw_power_reset);
462 void mx28_handle_5v_conflict(void)
464 struct mx28_power_regs *power_regs =
465 (struct mx28_power_regs *)MXS_POWER_BASE;
468 setbits_le32(&power_regs->hw_power_vddioctrl,
469 POWER_VDDIOCTRL_BO_OFFSET_MASK);
472 tmp = readl(&power_regs->hw_power_sts);
474 if (tmp & POWER_STS_VDDIO_BO) {
479 if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
480 mx28_boot_valid_5v();
489 int mx28_get_batt_volt(void)
491 struct mx28_power_regs *power_regs =
492 (struct mx28_power_regs *)MXS_POWER_BASE;
493 uint32_t volt = readl(&power_regs->hw_power_battmonitor);
494 volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
495 volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
500 int mx28_is_batt_ready(void)
502 return (mx28_get_batt_volt() >= 3600);
505 void mx28_5v_boot(void)
507 struct mx28_power_regs *power_regs =
508 (struct mx28_power_regs *)MXS_POWER_BASE;
511 * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
512 * but their implementation always returns 1 so we omit it here.
514 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
515 mx28_boot_valid_5v();
520 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
521 mx28_boot_valid_5v();
525 mx28_handle_5v_conflict();
528 void mx28_init_batt_bo(void)
530 struct mx28_power_regs *power_regs =
531 (struct mx28_power_regs *)MXS_POWER_BASE;
534 clrsetbits_le32(&power_regs->hw_power_battmonitor,
535 POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
536 15 << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
538 writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
539 writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
542 void mx28_switch_vddd_to_dcdc_source(void)
544 struct mx28_power_regs *power_regs =
545 (struct mx28_power_regs *)MXS_POWER_BASE;
547 clrsetbits_le32(&power_regs->hw_power_vdddctrl,
548 POWER_VDDDCTRL_LINREG_OFFSET_MASK,
549 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
551 clrbits_le32(&power_regs->hw_power_vdddctrl,
552 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
553 POWER_VDDDCTRL_DISABLE_STEPPING);
556 int mx28_is_batt_good(void)
558 struct mx28_power_regs *power_regs =
559 (struct mx28_power_regs *)MXS_POWER_BASE;
562 volt = readl(&power_regs->hw_power_battmonitor);
563 volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
564 volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
567 if ((volt >= 2400) && (volt <= 4300))
570 clrsetbits_le32(&power_regs->hw_power_5vctrl,
571 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
572 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
573 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
574 &power_regs->hw_power_5vctrl_clr);
576 clrsetbits_le32(&power_regs->hw_power_charge,
577 POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
578 POWER_CHARGE_STOP_ILIMIT_10MA | 0x3);
580 writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr);
581 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
582 &power_regs->hw_power_5vctrl_clr);
586 volt = readl(&power_regs->hw_power_battmonitor);
587 volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
588 volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
597 writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
598 &power_regs->hw_power_charge_clr);
599 writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
604 void mx28_power_configure_power_source(void)
606 mx28_src_power_init();
609 mx28_power_clock2pll();
612 mx28_switch_vddd_to_dcdc_source();
615 void mx28_enable_output_rail_protection(void)
617 struct mx28_power_regs *power_regs =
618 (struct mx28_power_regs *)MXS_POWER_BASE;
620 writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
621 POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
623 setbits_le32(&power_regs->hw_power_vdddctrl,
624 POWER_VDDDCTRL_PWDN_BRNOUT);
626 setbits_le32(&power_regs->hw_power_vddactrl,
627 POWER_VDDACTRL_PWDN_BRNOUT);
629 setbits_le32(&power_regs->hw_power_vddioctrl,
630 POWER_VDDIOCTRL_PWDN_BRNOUT);
633 int mx28_get_vddio_power_source_off(void)
635 struct mx28_power_regs *power_regs =
636 (struct mx28_power_regs *)MXS_POWER_BASE;
639 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
640 tmp = readl(&power_regs->hw_power_vddioctrl);
641 if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
642 if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
643 POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
648 if (!(readl(&power_regs->hw_power_5vctrl) &
649 POWER_5VCTRL_ENABLE_DCDC)) {
650 if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
651 POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
661 int mx28_get_vddd_power_source_off(void)
663 struct mx28_power_regs *power_regs =
664 (struct mx28_power_regs *)MXS_POWER_BASE;
667 tmp = readl(&power_regs->hw_power_vdddctrl);
668 if (tmp & POWER_VDDDCTRL_DISABLE_FET) {
669 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
670 POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
675 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
676 if (!(readl(&power_regs->hw_power_5vctrl) &
677 POWER_5VCTRL_ENABLE_DCDC)) {
682 if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) {
683 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
684 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) {
692 void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout)
694 struct mx28_power_regs *power_regs =
695 (struct mx28_power_regs *)MXS_POWER_BASE;
696 uint32_t cur_target, diff, bo_int = 0;
697 uint32_t powered_by_linreg = 0;
699 new_brownout = new_target - new_brownout;
701 cur_target = readl(&power_regs->hw_power_vddioctrl);
702 cur_target &= POWER_VDDIOCTRL_TRG_MASK;
703 cur_target *= 50; /* 50 mV step*/
704 cur_target += 2800; /* 2800 mV lowest */
706 powered_by_linreg = mx28_get_vddio_power_source_off();
707 if (new_target > cur_target) {
709 if (powered_by_linreg) {
710 bo_int = readl(&power_regs->hw_power_vddioctrl);
711 clrbits_le32(&power_regs->hw_power_vddioctrl,
712 POWER_CTRL_ENIRQ_VDDIO_BO);
715 setbits_le32(&power_regs->hw_power_vddioctrl,
716 POWER_VDDIOCTRL_BO_OFFSET_MASK);
718 if (new_target - cur_target > 100)
719 diff = cur_target + 100;
726 clrsetbits_le32(&power_regs->hw_power_vddioctrl,
727 POWER_VDDIOCTRL_TRG_MASK, diff);
729 if (powered_by_linreg)
732 while (!(readl(&power_regs->hw_power_sts) &
738 cur_target = readl(&power_regs->hw_power_vddioctrl);
739 cur_target &= POWER_VDDIOCTRL_TRG_MASK;
740 cur_target *= 50; /* 50 mV step*/
741 cur_target += 2800; /* 2800 mV lowest */
742 } while (new_target > cur_target);
744 if (powered_by_linreg) {
745 writel(POWER_CTRL_VDDIO_BO_IRQ,
746 &power_regs->hw_power_ctrl_clr);
747 if (bo_int & POWER_CTRL_ENIRQ_VDDIO_BO)
748 setbits_le32(&power_regs->hw_power_vddioctrl,
749 POWER_CTRL_ENIRQ_VDDIO_BO);
753 if (cur_target - new_target > 100)
754 diff = cur_target - 100;
761 clrsetbits_le32(&power_regs->hw_power_vddioctrl,
762 POWER_VDDIOCTRL_TRG_MASK, diff);
764 if (powered_by_linreg)
767 while (!(readl(&power_regs->hw_power_sts) &
773 cur_target = readl(&power_regs->hw_power_vddioctrl);
774 cur_target &= POWER_VDDIOCTRL_TRG_MASK;
775 cur_target *= 50; /* 50 mV step*/
776 cur_target += 2800; /* 2800 mV lowest */
777 } while (new_target < cur_target);
780 clrsetbits_le32(&power_regs->hw_power_vddioctrl,
781 POWER_VDDDCTRL_BO_OFFSET_MASK,
782 new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET);
785 void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout)
787 struct mx28_power_regs *power_regs =
788 (struct mx28_power_regs *)MXS_POWER_BASE;
789 uint32_t cur_target, diff, bo_int = 0;
790 uint32_t powered_by_linreg = 0;
792 new_brownout = new_target - new_brownout;
794 cur_target = readl(&power_regs->hw_power_vdddctrl);
795 cur_target &= POWER_VDDDCTRL_TRG_MASK;
796 cur_target *= 25; /* 25 mV step*/
797 cur_target += 800; /* 800 mV lowest */
799 powered_by_linreg = mx28_get_vddd_power_source_off();
800 if (new_target > cur_target) {
801 if (powered_by_linreg) {
802 bo_int = readl(&power_regs->hw_power_vdddctrl);
803 clrbits_le32(&power_regs->hw_power_vdddctrl,
804 POWER_CTRL_ENIRQ_VDDD_BO);
807 setbits_le32(&power_regs->hw_power_vdddctrl,
808 POWER_VDDDCTRL_BO_OFFSET_MASK);
811 if (new_target - cur_target > 100)
812 diff = cur_target + 100;
819 clrsetbits_le32(&power_regs->hw_power_vdddctrl,
820 POWER_VDDDCTRL_TRG_MASK, diff);
822 if (powered_by_linreg)
825 while (!(readl(&power_regs->hw_power_sts) &
831 cur_target = readl(&power_regs->hw_power_vdddctrl);
832 cur_target &= POWER_VDDDCTRL_TRG_MASK;
833 cur_target *= 25; /* 25 mV step*/
834 cur_target += 800; /* 800 mV lowest */
835 } while (new_target > cur_target);
837 if (powered_by_linreg) {
838 writel(POWER_CTRL_VDDD_BO_IRQ,
839 &power_regs->hw_power_ctrl_clr);
840 if (bo_int & POWER_CTRL_ENIRQ_VDDD_BO)
841 setbits_le32(&power_regs->hw_power_vdddctrl,
842 POWER_CTRL_ENIRQ_VDDD_BO);
846 if (cur_target - new_target > 100)
847 diff = cur_target - 100;
854 clrsetbits_le32(&power_regs->hw_power_vdddctrl,
855 POWER_VDDDCTRL_TRG_MASK, diff);
857 if (powered_by_linreg)
860 while (!(readl(&power_regs->hw_power_sts) &
866 cur_target = readl(&power_regs->hw_power_vdddctrl);
867 cur_target &= POWER_VDDDCTRL_TRG_MASK;
868 cur_target *= 25; /* 25 mV step*/
869 cur_target += 800; /* 800 mV lowest */
870 } while (new_target < cur_target);
873 clrsetbits_le32(&power_regs->hw_power_vdddctrl,
874 POWER_VDDDCTRL_BO_OFFSET_MASK,
875 new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET);
878 void mx28_power_init(void)
880 struct mx28_power_regs *power_regs =
881 (struct mx28_power_regs *)MXS_POWER_BASE;
883 mx28_power_clock2xtal();
884 mx28_power_clear_auto_restart();
885 mx28_power_set_linreg();
886 mx28_power_setup_5v_detect();
887 mx28_power_configure_power_source();
888 mx28_enable_output_rail_protection();
890 mx28_power_set_vddio(3300, 3150);
892 mx28_power_set_vddd(1350, 1200);
894 writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
895 POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
896 POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
897 POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
899 writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set);
904 #ifdef CONFIG_SPL_MX28_PSWITCH_WAIT
905 void mx28_power_wait_pswitch(void)
907 struct mx28_power_regs *power_regs =
908 (struct mx28_power_regs *)MXS_POWER_BASE;
910 while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))