git.sur5r.net Git - u-boot/blob - board/denx/m53evk/m53evk.c

   1 /*
   2  * DENX M53 module
   3  *
   4  * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/sys_proto.h>
  13 #include <asm/arch/crm_regs.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/iomux-mx53.h>
  16 #include <asm/arch/spl.h>
  17 #include <asm/errno.h>
  18 #include <netdev.h>
  19 #include <i2c.h>
  20 #include <mmc.h>
  21 #include <spl.h>
  22 #include <fsl_esdhc.h>
  23 #include <asm/gpio.h>
  24 #include <usb/ehci-fsl.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 int dram_init(void)
  29 {
  30         u32 size1, size2;
  31
  32         size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  33         size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
  34
  35         gd->ram_size = size1 + size2;
  36
  37         return 0;
  38 }
  39 void dram_init_banksize(void)
  40 {
  41         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  42         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  43
  44         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  45         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  46 }
  47
  48 static void setup_iomux_uart(void)
  49 {
  50         static const iomux_v3_cfg_t uart_pads[] = {
  51                 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
  52                 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
  53         };
  54
  55         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  56 }
  57
  58 #ifdef CONFIG_USB_EHCI_MX5
  59 int board_ehci_hcd_init(int port)
  60 {
  61         if (port == 0) {
  62                 /* USB OTG PWRON */
  63                 imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4,
  64                                         PAD_CTL_PKE | PAD_CTL_DSE_HIGH));
  65                 gpio_direction_output(IMX_GPIO_NR(1, 4), 0);
  66
  67                 /* USB OTG Over Current */
  68                 imx_iomux_v3_setup_pad(MX53_PAD_GPIO_18__GPIO7_13);
  69         } else if (port == 1) {
  70                 /* USB Host PWRON */
  71                 imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2,
  72                                         PAD_CTL_PKE | PAD_CTL_DSE_HIGH));
  73                 gpio_direction_output(IMX_GPIO_NR(1, 2), 0);
  74
  75                 /* USB Host Over Current */
  76                 imx_iomux_v3_setup_pad(MX53_PAD_GPIO_3__USBOH3_USBH1_OC);
  77         }
  78
  79         return 0;
  80 }
  81 #endif
  82
  83 static void setup_iomux_fec(void)
  84 {
  85         static const iomux_v3_cfg_t fec_pads[] = {
  86                 /* MDIO pads */
  87                 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
  88                         PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
  89                 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
  90
  91                 /* FEC 0 pads */
  92                 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
  93                                 PAD_CTL_HYS | PAD_CTL_PKE),
  94                 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
  95                                 PAD_CTL_HYS | PAD_CTL_PKE),
  96                 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
  97                                 PAD_CTL_HYS | PAD_CTL_PKE),
  98                 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
  99                 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
 100                                 PAD_CTL_HYS | PAD_CTL_PKE),
 101                 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
 102                                 PAD_CTL_HYS | PAD_CTL_PKE),
 103                 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
 104                 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
 105
 106                 /* FEC 1 pads */
 107                 NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
 108                                 PAD_CTL_HYS | PAD_CTL_PKE),
 109                 NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
 110                                 PAD_CTL_HYS | PAD_CTL_PKE),
 111                 NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
 112                                 PAD_CTL_HYS | PAD_CTL_PKE),
 113                 NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
 114                                 PAD_CTL_HYS | PAD_CTL_PKE),
 115                 NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
 116                                 PAD_CTL_HYS | PAD_CTL_PKE),
 117                 NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
 118                 NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
 119                                 PAD_CTL_HYS | PAD_CTL_PKE),
 120                 NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
 121         };
 122
 123         imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 124 }
 125
 126 #ifdef CONFIG_FSL_ESDHC
 127 struct fsl_esdhc_cfg esdhc_cfg = {
 128         MMC_SDHC1_BASE_ADDR,
 129 };
 130
 131 int board_mmc_getcd(struct mmc *mmc)
 132 {
 133         imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
 134         gpio_direction_input(IMX_GPIO_NR(1, 1));
 135
 136         return !gpio_get_value(IMX_GPIO_NR(1, 1));
 137 }
 138
 139 #define SD_CMD_PAD_CTRL         (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
 140                                  PAD_CTL_PUS_100K_UP)
 141 #define SD_PAD_CTRL             (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
 142                                  PAD_CTL_DSE_HIGH)
 143
 144 int board_mmc_init(bd_t *bis)
 145 {
 146         static const iomux_v3_cfg_t sd1_pads[] = {
 147                 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
 148                 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
 149                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
 150                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
 151                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
 152                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
 153                 MX53_PAD_EIM_DA13__GPIO3_13,
 154
 155                 MX53_PAD_EIM_EB3__GPIO2_31, /* SD power */
 156         };
 157
 158         esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 159
 160         imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
 161
 162         /* GPIO 2_31 is SD power */
 163         gpio_direction_output(IMX_GPIO_NR(2, 31), 0);
 164
 165         return fsl_esdhc_initialize(bis, &esdhc_cfg);
 166 }
 167 #endif
 168
 169 #define I2C_PAD_CTRL    (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
 170                          PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
 171
 172 static void setup_iomux_i2c(void)
 173 {
 174         static const iomux_v3_cfg_t i2c_pads[] = {
 175                 NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
 176                 NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
 177         };
 178
 179         imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
 180 }
 181
 182 static void setup_iomux_nand(void)
 183 {
 184         static const iomux_v3_cfg_t nand_pads[] = {
 185                 NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
 186                                 PAD_CTL_DSE_HIGH),
 187                 NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
 188                                 PAD_CTL_DSE_HIGH),
 189                 NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
 190                                 PAD_CTL_DSE_HIGH),
 191                 NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
 192                                 PAD_CTL_DSE_HIGH),
 193                 NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
 194                                 PAD_CTL_PUS_100K_UP),
 195                 NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
 196                                 PAD_CTL_PUS_100K_UP),
 197                 NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
 198                                 PAD_CTL_DSE_HIGH),
 199                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
 200                                 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 201                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
 202                                 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 203                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
 204                                 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 205                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
 206                                 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 207                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
 208                                 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 209                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
 210                                 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 211                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
 212                                 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 213                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
 214                                 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 215         };
 216
 217         imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
 218 }
 219
 220 static void m53_set_clock(void)
 221 {
 222         int ret;
 223         const uint32_t ref_clk = MXC_HCLK;
 224         const uint32_t dramclk = 400;
 225         uint32_t cpuclk;
 226
 227         imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
 228                                             PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
 229         gpio_direction_input(IMX_GPIO_NR(4, 0));
 230
 231         /* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
 232         cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;
 233
 234         ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
 235         if (ret)
 236                 printf("CPU:   Switch CPU clock to %dMHz failed\n", cpuclk);
 237
 238         ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
 239         if (ret) {
 240                 printf("CPU:   Switch peripheral clock to %dMHz failed\n",
 241                         dramclk);
 242         }
 243
 244         ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
 245         if (ret)
 246                 printf("CPU:   Switch DDR clock to %dMHz failed\n", dramclk);
 247 }
 248
 249 static void m53_set_nand(void)
 250 {
 251         u32 i;
 252
 253         /* NAND flash is muxed on ATA pins */
 254         setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);
 255
 256         /* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
 257         for (i = 0x4; i < 0x94; i += 0x18) {
 258                 clrbits_le32(WEIM_BASE_ADDR + i,
 259                              WEIM_GCR2_MUX16_BYP_GRANT_MASK);
 260         }
 261
 262         mxc_set_clock(0, 33, MXC_NFC_CLK);
 263         enable_nfc_clk(1);
 264 }
 265
 266 int board_early_init_f(void)
 267 {
 268         setup_iomux_uart();
 269         setup_iomux_fec();
 270         setup_iomux_i2c();
 271         setup_iomux_nand();
 272
 273         m53_set_clock();
 274
 275         mxc_set_sata_internal_clock();
 276
 277         /* NAND clock @ 33MHz */
 278         m53_set_nand();
 279
 280         return 0;
 281 }
 282
 283 int board_init(void)
 284 {
 285         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 286
 287         return 0;
 288 }
 289
 290 int checkboard(void)
 291 {
 292         puts("Board: DENX M53EVK\n");
 293
 294         return 0;
 295 }
 296
 297 /*
 298  * NAND SPL
 299  */
 300 #ifdef CONFIG_SPL_BUILD
 301 void spl_board_init(void)
 302 {
 303         setup_iomux_nand();
 304         m53_set_clock();
 305         m53_set_nand();
 306 }
 307
 308 u32 spl_boot_device(void)
 309 {
 310         return BOOT_DEVICE_NAND;
 311 }
 312 #endif