3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * (C) Copyright 2005-2009
9 * Modified for InterControl digsyMTC MPC5200 board by
10 * Frank Bodammer, GCD Hard- & Software GmbH,
11 * frank.bodammer@gcd-solutions.de
14 * Grzegorz Bernacki, Semihalf, gjb@semihalf.com
16 * See file CREDITS for list of people who contributed to this
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
39 #include <asm/processor.h>
42 #if defined(CONFIG_DIGSY_REV5)
43 #include "is45s16800a2.h"
44 #include <mtd/cfi_flash.h>
47 #include "is42s16800a-7t.h"
50 #include <fdt_support.h>
52 DECLARE_GLOBAL_DATA_PTR;
54 extern int usb_cpu_init(void);
56 #if defined(CONFIG_DIGSY_REV5)
58 * The M29W128GH needs a specail reset command function,
59 * details see the doc/README.cfi file
61 void flash_cmd_reset(flash_info_t *info)
63 flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
67 #ifndef CONFIG_SYS_RAMBOOT
68 static void sdram_start(int hi_addr)
70 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
71 long control = SDRAM_CONTROL | hi_addr_bit;
73 /* unlock mode register */
74 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
76 /* precharge all banks */
77 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
80 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
82 /* set mode register */
83 out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
85 /* normal operation */
86 out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
91 * ATTENTION: Although partially referenced initdram does NOT make real use
92 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
93 * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
96 phys_size_t initdram(int board_type)
101 #ifndef CONFIG_SYS_RAMBOOT
104 /* setup SDRAM chip selects */
105 out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001C); /* 512MB at 0x0 */
106 out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
108 /* setup config registers */
109 out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
110 out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
112 /* find RAM size using SDRAM CS0 only */
114 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
116 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
124 /* memory smaller than 1MB is impossible */
125 if (dramsize < (1 << 20))
128 /* set SDRAM CS0 size according to the amount of RAM found */
130 out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
131 (0x13 + __builtin_ffs(dramsize >> 20) - 1));
133 out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
136 /* let SDRAM CS1 start right after CS0 */
137 out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize + 0x0000001C);
139 /* find RAM size using SDRAM CS1 only */
140 test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
144 /* memory smaller than 1MB is impossible */
145 if (dramsize2 < (1 << 20))
148 /* set SDRAM CS1 size according to the amount of RAM found */
150 out_be32((void *)MPC5XXX_SDRAM_CS1CFG, (dramsize |
151 (0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
153 out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */
156 #else /* CONFIG_SYS_RAMBOOT */
158 /* retrieve size of memory connected to SDRAM CS0 */
159 dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
160 if (dramsize >= 0x13)
161 dramsize = (1 << (dramsize - 0x13)) << 20;
165 /* retrieve size of memory connected to SDRAM CS1 */
166 dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
167 if (dramsize2 >= 0x13)
168 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
172 #endif /* CONFIG_SYS_RAMBOOT */
175 * On MPC5200B we need to set the special configuration delay in the
176 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
177 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
179 * "The SDelay should be written to a value of 0x00000004. It is
180 * required to account for changes caused by normal wafer processing
185 if ((SVR_MJREV(svr) >= 2) &&
186 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
187 out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
189 return dramsize + dramsize2;
194 char *s = getenv("serial#");
196 puts ("Board: InterControl digsyMTC");
197 #if defined(CONFIG_DIGSY_REV5)
209 int board_early_init_r(void)
211 #ifdef CONFIG_MPC52XX_SPI
212 struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt*)MPC5XXX_GPT;
215 * Now, when we are in RAM, enable flash write access for detection
216 * process. Note that CS_BOOT cannot be cleared when executing in
219 /* disable CS_BOOT */
220 clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));
222 setbits_be32((void *)MPC5XXX_ADDECR, (1 << 17));
224 setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));
226 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
227 /* Low level USB init, required for proper kernel operation */
230 #ifdef CONFIG_MPC52XX_SPI
231 /* GPT 6 Output Enable */
232 out_be32(&gpt[6].emsr, 0x00000034);
233 /* GPT 7 Output Enable */
234 out_be32(&gpt[7].emsr, 0x00000034);
240 void board_get_enetaddr (uchar * enet)
243 ushort addr_of_eth_addr = 0;
245 ushort len_sys_cfg = 0;
247 /* check identification word */
248 eeprom_read(EEPROM_ADDR, EEPROM_ADDR_IDENT, (uchar *)&read, 2);
249 if (read != EEPROM_IDENT)
252 /* calculate offset of config area */
253 eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYS, (uchar *)&len_sys, 2);
254 eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYSCFG,
255 (uchar *)&len_sys_cfg, 2);
256 addr_of_eth_addr = (len_sys + len_sys_cfg + EEPROM_ADDR_ETHADDR) << 1;
257 if (addr_of_eth_addr >= EEPROM_LEN)
260 eeprom_read(EEPROM_ADDR, addr_of_eth_addr, enet, 6);
263 int misc_init_r(void)
267 if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
268 board_get_enetaddr(enetaddr);
269 eth_setenv_enetaddr("ethaddr", enetaddr);
276 static struct pci_controller hose;
278 extern void pci_mpc5xxx_init(struct pci_controller *);
280 void pci_init_board(void)
282 pci_mpc5xxx_init(&hose);
286 #ifdef CONFIG_CMD_IDE
288 #ifdef CONFIG_IDE_RESET
290 void init_ide_reset(void)
292 debug ("init_ide_reset\n");
294 /* set gpio output value to 1 */
295 setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
296 /* open drain output */
297 setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
298 /* direction output */
299 setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
301 setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
305 void ide_set_reset(int idereset)
307 debug ("ide_reset(%d)\n", idereset);
309 /* set gpio output value to 0 */
310 clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
311 /* open drain output */
312 setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
313 /* direction output */
314 setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
316 setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
320 /* set gpio output value to 1 */
321 setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
322 /* open drain output */
323 setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
324 /* direction output */
325 setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
327 setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
329 #endif /* CONFIG_IDE_RESET */
330 #endif /* CONFIG_CMD_IDE */
332 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
333 static void ft_delete_node(void *fdt, const char *compat)
338 off = fdt_node_offset_by_compatible(fdt, -1, compat);
340 printf("Could not find %s node.\n", compat);
344 ret = fdt_del_node(fdt, off);
346 printf("Could not delete %s node.\n", compat);
348 #if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
349 static void ft_adapt_flash_base(void *blob)
351 flash_info_t *dev = &flash_info[0];
353 struct fdt_property *prop;
357 off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");
359 printf("Could not find fsl,mpc5200b-lpb node.\n");
363 /* found compatible property */
364 prop = fdt_get_property_w(blob, off, "ranges", &len);
366 reg = reg2 = (u32 *)&prop->data[0];
368 reg[2] = dev->start[0];
370 fdt_setprop(blob, off, "ranges", reg2, len);
372 printf("Could not find ranges\n");
375 extern ulong flash_get_size (phys_addr_t base, int banknum);
377 /* Update the Flash Baseaddr settings */
378 int update_flash_size (int flash_size)
380 volatile struct mpc5xxx_mmap_ctl *mm =
381 (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
385 unsigned long base = 0x0;
386 u32 *cs_reg = (u32 *)&mm->cs0_start;
388 for (i = 0; i < 2; i++) {
389 dev = &flash_info[i];
392 /* calculate new base addr for this chipselect */
394 out_be32(cs_reg, START_REG(base));
396 out_be32(cs_reg, STOP_REG(base, dev->size));
398 /* recalculate the sectoraddr in the cfi driver */
399 size += flash_get_size(base, i);
402 flash_protect_default();
403 gd->bd->bi_flashstart = base;
406 #endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
408 void ft_board_setup(void *blob, bd_t *bd)
410 int phy_addr = CONFIG_PHY_ADDR;
411 char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";
413 ft_cpu_setup(blob, bd);
415 * There are 2 RTC nodes in the DTS, so remove
416 * the unneeded node here.
418 #if defined(CONFIG_DIGSY_REV5)
419 ft_delete_node(blob, "dallas,ds1339");
421 ft_delete_node(blob, "mc,rv3029c2");
423 #if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
424 #ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
425 /* Update reg property in all nor flash nodes too */
426 fdt_fixup_nor_flash_size(blob);
428 ft_adapt_flash_base(blob);
430 /* fix up the phy address */
431 do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0);
433 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */