git.sur5r.net Git - u-boot/blob - board/eNET/eNET.c

   1 /*
   2  * (C) Copyright 2008
   3  * Graeme Russ, graeme.russ@gmail.com.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/io.h>
  26 #include <asm/ic/sc520.h>
  27 #include <net.h>
  28 #include <netdev.h>
  29
  30 #ifdef CONFIG_HW_WATCHDOG
  31 #include <watchdog.h>
  32 #endif
  33
  34 #include "hardware.h"
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 #undef SC520_CDP_DEBUG
  39
  40 #ifdef  SC520_CDP_DEBUG
  41 #define PRINTF(fmt,args...)     printf (fmt ,##args)
  42 #else
  43 #define PRINTF(fmt,args...)
  44 #endif
  45
  46 unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
  47
  48 static void enet_timer_isr(void);
  49 static void enet_toggle_run_led(void);
  50
  51 /*
  52  * Miscellaneous platform dependent initializations
  53  */
  54 int board_early_init_f(void)
  55 {
  56         u16 pio_out_cfg = 0x0000;
  57
  58         /* Configure General Purpose Bus timing */
  59         writeb(CONFIG_SYS_SC520_GPCSRT, &sc520_mmcr->gpcsrt);
  60         writeb(CONFIG_SYS_SC520_GPCSPW, &sc520_mmcr->gpcspw);
  61         writeb(CONFIG_SYS_SC520_GPCSOFF, &sc520_mmcr->gpcsoff);
  62         writeb(CONFIG_SYS_SC520_GPRDW, &sc520_mmcr->gprdw);
  63         writeb(CONFIG_SYS_SC520_GPRDOFF, &sc520_mmcr->gprdoff);
  64         writeb(CONFIG_SYS_SC520_GPWRW, &sc520_mmcr->gpwrw);
  65         writeb(CONFIG_SYS_SC520_GPWROFF, &sc520_mmcr->gpwroff);
  66
  67         /* Configure Programmable Input/Output Pins */
  68         writew(CONFIG_SYS_SC520_PIODIR15_0, &sc520_mmcr->piodir15_0);
  69         writew(CONFIG_SYS_SC520_PIODIR31_16, &sc520_mmcr->piodir31_16);
  70         writew(CONFIG_SYS_SC520_PIOPFS31_16, &sc520_mmcr->piopfs31_16);
  71         writew(CONFIG_SYS_SC520_PIOPFS15_0, &sc520_mmcr->piopfs15_0);
  72         writeb(CONFIG_SYS_SC520_CSPFS, &sc520_mmcr->cspfs);
  73         writeb(CONFIG_SYS_SC520_CLKSEL, &sc520_mmcr->clksel);
  74
  75         /*
  76          * Turn off top board
  77          * Set StrataFlash chips to 16-bit width
  78          * Set StrataFlash chips to normal (non reset/power down) mode
  79          */
  80         pio_out_cfg |= CONFIG_SYS_ENET_TOP_BRD_PWR;
  81         pio_out_cfg |= CONFIG_SYS_ENET_SF_WIDTH;
  82         pio_out_cfg |= CONFIG_SYS_ENET_SF1_MODE;
  83         pio_out_cfg |= CONFIG_SYS_ENET_SF2_MODE;
  84         writew(pio_out_cfg, &sc520_mmcr->pioset15_0);
  85
  86         /* Turn off auxiliary power output */
  87         writew(CONFIG_SYS_ENET_AUX_PWR, &sc520_mmcr->pioclr15_0);
  88
  89         /* Clear FPGA program mode */
  90         writew(CONFIG_SYS_ENET_FPGA_PROG, &sc520_mmcr->pioset31_16);
  91
  92         /* Configure Programmable Address Regions */
  93         writel(CONFIG_SYS_SC520_UARTA_PAR, &sc520_mmcr->par[2]);
  94         writel(CONFIG_SYS_SC520_UARTB_PAR, &sc520_mmcr->par[3]);
  95         writel(CONFIG_SYS_SC520_UARTC_PAR, &sc520_mmcr->par[4]);
  96         writel(CONFIG_SYS_SC520_UARTD_PAR, &sc520_mmcr->par[5]);
  97         writel(CONFIG_SYS_SC520_SDRAM_PAR, &sc520_mmcr->par[6]);
  98         writel(CONFIG_SYS_SC520_SF1_PAR, &sc520_mmcr->par[7]);
  99         writel(CONFIG_SYS_SC520_SF2_PAR, &sc520_mmcr->par[8]);
 100         writel(CONFIG_SYS_SC520_SRAM1_PAR, &sc520_mmcr->par[9]);
 101         writel(CONFIG_SYS_SC520_SRAM2_PAR, &sc520_mmcr->par[10]);
 102         writel(CONFIG_SYS_SC520_DPRAM_PAR, &sc520_mmcr->par[11]);
 103         writel(CONFIG_SYS_SC520_CF1_PAR, &sc520_mmcr->par[12]);
 104         writel(CONFIG_SYS_SC520_CF2_PAR, &sc520_mmcr->par[13]);
 105 /*      writel(CONFIG_SYS_SC520_BOOTCS_PAR, &sc520_mmcr->par14); */
 106 /*      writel(CONFIG_SYS_SC520_LLIO_PAR, &sc520_mmcr->par15); */
 107
 108         /* Disable Watchdog */
 109         writew(0x3333, &sc520_mmcr->wdtmrctl);
 110         writew(0xcccc, &sc520_mmcr->wdtmrctl);
 111         writew(0x0000, &sc520_mmcr->wdtmrctl);
 112
 113         /* Chip Select Configuration */
 114         writew(CONFIG_SYS_SC520_BOOTCS_CTRL, &sc520_mmcr->bootcsctl);
 115         writew(CONFIG_SYS_SC520_ROMCS1_CTRL, &sc520_mmcr->romcs1ctl);
 116         writew(CONFIG_SYS_SC520_ROMCS2_CTRL, &sc520_mmcr->romcs2ctl);
 117
 118         writeb(CONFIG_SYS_SC520_ADDDECCTL, &sc520_mmcr->adddecctl);
 119         writeb(CONFIG_SYS_SC520_UART1CTL, &sc520_mmcr->uart1ctl);
 120         writeb(CONFIG_SYS_SC520_UART2CTL, &sc520_mmcr->uart2ctl);
 121
 122         writeb(CONFIG_SYS_SC520_SYSARBCTL, &sc520_mmcr->sysarbctl);
 123         writew(CONFIG_SYS_SC520_SYSARBMENB, &sc520_mmcr->sysarbmenb);
 124
 125         /* enable posted-writes */
 126         writeb(CONFIG_SYS_SC520_HBCTL, &sc520_mmcr->hbctl);
 127
 128         return 0;
 129 }
 130
 131 int board_early_init_r(void)
 132 {
 133         /* CPU Speed to 100MHz */
 134         gd->cpu_clk = 100000000;
 135
 136         /* Crystal is 33.000MHz */
 137         gd->bus_clk = 33000000;
 138
 139         return 0;
 140 }
 141
 142 int dram_init(void)
 143 {
 144         init_sc520_dram();
 145         return 0;
 146 }
 147
 148 void show_boot_progress(int val)
 149 {
 150         uchar led_mask;
 151
 152         led_mask = 0x00;
 153
 154         if (val < 0)
 155                 led_mask |= LED_ERR_BITMASK;
 156
 157         led_mask |= (uchar)(val & 0x001f);
 158         outb(led_mask, LED_LATCH_ADDRESS);
 159 }
 160
 161
 162 int last_stage_init(void)
 163 {
 164         int minor;
 165         int major;
 166
 167         major = minor = 0;
 168
 169         outb(0x00, LED_LATCH_ADDRESS);
 170
 171         register_timer_isr (enet_timer_isr);
 172
 173         printf("Serck Controls eNET\n");
 174
 175         return 0;
 176 }
 177
 178 ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
 179 {
 180         if (banknum == 0) {     /* non-CFI boot flash */
 181                 info->portwidth = FLASH_CFI_8BIT;
 182                 info->chipwidth = FLASH_CFI_BY8;
 183                 info->interface = FLASH_CFI_X8;
 184                 return 1;
 185         } else
 186                 return 0;
 187 }
 188
 189 int board_eth_init(bd_t *bis)
 190 {
 191         return pci_eth_init(bis);
 192 }
 193
 194 void setup_pcat_compatibility()
 195 {
 196         /* disable global interrupt mode */
 197         writeb(0x40, &sc520_mmcr->picicr);
 198
 199         /* set all irqs to edge */
 200         writeb(0x00, &sc520_mmcr->pic_mode[0]);
 201         writeb(0x00, &sc520_mmcr->pic_mode[1]);
 202         writeb(0x00, &sc520_mmcr->pic_mode[2]);
 203
 204         /*
 205          *  active low polarity on PIC interrupt pins,
 206          *  active high polarity on all other irq pins
 207          */
 208         writew(0x0000,&sc520_mmcr->intpinpol);
 209
 210         /*
 211          * PIT 0 -> IRQ0
 212          * RTC -> IRQ8
 213          * FP error -> IRQ13
 214          * UART1 -> IRQ4
 215          * UART2 -> IRQ3
 216          */
 217         writeb(SC520_IRQ0, &sc520_mmcr->pit_int_map[0]);
 218         writeb(SC520_IRQ8, &sc520_mmcr->rtcmap);
 219         writeb(SC520_IRQ13, &sc520_mmcr->ferrmap);
 220         writeb(SC520_IRQ4, &sc520_mmcr->uart_int_map[0]);
 221         writeb(SC520_IRQ3, &sc520_mmcr->uart_int_map[1]);
 222
 223         /* Disable all other interrupt sources */
 224         writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[0]);
 225         writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[1]);
 226         writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[2]);
 227         writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[1]);
 228         writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[2]);
 229         writeb(SC520_IRQ_DISABLED, &sc520_mmcr->ssimap);
 230         writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wdtmap);
 231         writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wpvmap);
 232         writeb(SC520_IRQ_DISABLED, &sc520_mmcr->icemap);
 233 }
 234
 235 void enet_timer_isr(void)
 236 {
 237         static long enet_ticks = 0;
 238
 239         enet_ticks++;
 240
 241         /* Toggle Watchdog every 100ms */
 242         if ((enet_ticks % 100) == 0)
 243                 hw_watchdog_reset();
 244
 245         /* Toggle Run LED every 500ms */
 246         if ((enet_ticks % 500) == 0)
 247                 enet_toggle_run_led();
 248 }
 249
 250 void hw_watchdog_reset(void)
 251 {
 252         /* Watchdog Reset must be atomic */
 253         long flag = disable_interrupts();
 254
 255         if (sc520_mmcr->piodata15_0 & WATCHDOG_PIO_BIT)
 256                 sc520_mmcr->pioclr15_0 = WATCHDOG_PIO_BIT;
 257         else
 258                 sc520_mmcr->pioset15_0 = WATCHDOG_PIO_BIT;
 259
 260         if (flag)
 261                 enable_interrupts();
 262 }
 263
 264 void enet_toggle_run_led(void)
 265 {
 266         unsigned char leds_state= inb(LED_LATCH_ADDRESS);
 267         if (leds_state & LED_RUN_BITMASK)
 268                 outb(leds_state &~ LED_RUN_BITMASK, LED_LATCH_ADDRESS);
 269         else
 270                 outb(leds_state | LED_RUN_BITMASK, LED_LATCH_ADDRESS);
 271 }