3 * Graeme Russ, graeme.russ@gmail.com.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/ic/sc520.h>
30 #ifdef CONFIG_HW_WATCHDOG
36 DECLARE_GLOBAL_DATA_PTR;
38 #undef SC520_CDP_DEBUG
40 #ifdef SC520_CDP_DEBUG
41 #define PRINTF(fmt,args...) printf (fmt ,##args)
43 #define PRINTF(fmt,args...)
46 unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
48 void init_sc520_enet (void)
50 /* Set CPU Speed to 100MHz */
51 writeb(0x01, &sc520_mmcr->cpuctl);
53 /* wait at least one millisecond */
54 asm("movl $0x2000,%%ecx\n"
57 "loop 0b\n": : : "ecx");
59 /* turn on the SDRAM write buffer */
60 writeb(0x11, &sc520_mmcr->dbctl);
62 /* turn on the cache and disable write through */
63 asm("movl %%cr0, %%eax\n"
64 "andl $0x9fffffff, %%eax\n"
65 "movl %%eax, %%cr0\n" : : : "eax");
69 * Miscellaneous platform dependent initializations
71 int board_early_init_f(void)
75 writeb(0x01, &sc520_mmcr->gpcsrt); /* GP Chip Select Recovery Time */
76 writeb(0x07, &sc520_mmcr->gpcspw); /* GP Chip Select Pulse Width */
77 writeb(0x00, &sc520_mmcr->gpcsoff); /* GP Chip Select Offset */
78 writeb(0x05, &sc520_mmcr->gprdw); /* GP Read pulse width */
79 writeb(0x01, &sc520_mmcr->gprdoff); /* GP Read offset */
80 writeb(0x05, &sc520_mmcr->gpwrw); /* GP Write pulse width */
81 writeb(0x01, &sc520_mmcr->gpwroff); /* GP Write offset */
83 writew(0x0630, &sc520_mmcr->piodata15_0); /* PIO15_PIO0 Data */
84 writew(0x2000, &sc520_mmcr->piodata31_16); /* PIO31_PIO16 Data */
85 writew(0x2000, &sc520_mmcr->piodir31_16); /* GPIO Direction */
86 writew(0x87b5, &sc520_mmcr->piodir15_0); /* GPIO Direction */
87 writew(0x0dfe, &sc520_mmcr->piopfs31_16); /* GPIO pin function 31-16 reg */
88 writew(0x200a, &sc520_mmcr->piopfs15_0); /* GPIO pin function 15-0 reg */
89 writeb(0xf8, &sc520_mmcr->cspfs); /* Chip Select Pin Function Select */
91 writel(0x200713f8, &sc520_mmcr->par[2]); /* Uart A (GPCS0, 0x013f8, 8 Bytes) */
92 writel(0x2c0712f8, &sc520_mmcr->par[3]); /* Uart B (GPCS3, 0x012f8, 8 Bytes) */
93 writel(0x300711f8, &sc520_mmcr->par[4]); /* Uart C (GPCS4, 0x011f8, 8 Bytes) */
94 writel(0x340710f8, &sc520_mmcr->par[5]); /* Uart D (GPCS5, 0x010f8, 8 Bytes) */
95 writel(0xe3ffc000, &sc520_mmcr->par[6]); /* SDRAM (0x00000000, 128MB) */
96 writel(0xaa3fd000, &sc520_mmcr->par[7]); /* StrataFlash (ROMCS1, 0x10000000, 16MB) */
97 writel(0xca3fd100, &sc520_mmcr->par[8]); /* StrataFlash (ROMCS2, 0x11000000, 16MB) */
98 writel(0x4203d900, &sc520_mmcr->par[9]); /* SRAM (GPCS0, 0x19000000, 1MB) */
99 writel(0x4e03d910, &sc520_mmcr->par[10]); /* SRAM (GPCS3, 0x19100000, 1MB) */
100 writel(0x50018100, &sc520_mmcr->par[11]); /* DP-RAM (GPCS4, 0x18100000, 4kB) */
101 writel(0x54020000, &sc520_mmcr->par[12]); /* CFLASH1 (0x200000000, 4kB) */
102 writel(0x5c020001, &sc520_mmcr->par[13]); /* CFLASH2 (0x200010000, 4kB) */
103 /* writel(0x8bfff800, &sc520_mmcr->par14); */ /* BOOTCS at 0x18000000 */
104 /* writel(0x38201000, &sc520_mmcr->par15); */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */
106 /* Disable Watchdog */
107 writew(0x3333, &sc520_mmcr->wdtmrctl);
108 writew(0xcccc, &sc520_mmcr->wdtmrctl);
109 writew(0x0000, &sc520_mmcr->wdtmrctl);
111 /* Chip Select Configuration */
112 writew(0x0033, &sc520_mmcr->bootcsctl);
113 writew(0x0615, &sc520_mmcr->romcs1ctl);
114 writew(0x0615, &sc520_mmcr->romcs2ctl);
116 writeb(0x00, &sc520_mmcr->adddecctl);
117 writeb(0x07, &sc520_mmcr->uart1ctl);
118 writeb(0x07, &sc520_mmcr->uart2ctl);
119 writeb(0x06, &sc520_mmcr->sysarbctl);
120 writew(0x0003, &sc520_mmcr->sysarbmenb);
125 int board_early_init_r(void)
127 /* CPU Speed to 100MHz */
128 gd->cpu_clk = 100000000;
130 /* Crystal is 33.000MHz */
131 gd->bus_clk = 33000000;
142 void show_boot_progress(int val)
149 led_mask |= LED_ERR_BITMASK;
151 led_mask |= (uchar)(val & 0x001f);
152 outb(led_mask, LED_LATCH_ADDRESS);
156 int last_stage_init(void)
163 printf("Serck Controls eNET\n");
168 ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
170 if (banknum == 0) { /* non-CFI boot flash */
171 info->portwidth = FLASH_CFI_8BIT;
172 info->chipwidth = FLASH_CFI_BY8;
173 info->interface = FLASH_CFI_X8;
179 int board_eth_init(bd_t *bis)
181 return pci_eth_init(bis);