3 * Graeme Russ, graeme.russ@gmail.com.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/ic/sc520.h>
30 #ifdef CONFIG_HW_WATCHDOG
36 DECLARE_GLOBAL_DATA_PTR;
38 #undef SC520_CDP_DEBUG
40 #ifdef SC520_CDP_DEBUG
41 #define PRINTF(fmt,args...) printf (fmt ,##args)
43 #define PRINTF(fmt,args...)
46 unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
48 static void enet_timer_isr(void);
49 static void enet_toggle_run_led(void);
52 * Miscellaneous platform dependent initializations
54 int board_early_init_f(void)
56 writeb(0x01, &sc520_mmcr->gpcsrt); /* GP Chip Select Recovery Time */
57 writeb(0x07, &sc520_mmcr->gpcspw); /* GP Chip Select Pulse Width */
58 writeb(0x00, &sc520_mmcr->gpcsoff); /* GP Chip Select Offset */
59 writeb(0x05, &sc520_mmcr->gprdw); /* GP Read pulse width */
60 writeb(0x01, &sc520_mmcr->gprdoff); /* GP Read offset */
61 writeb(0x05, &sc520_mmcr->gpwrw); /* GP Write pulse width */
62 writeb(0x01, &sc520_mmcr->gpwroff); /* GP Write offset */
64 writew(0x0630, &sc520_mmcr->piodata15_0); /* PIO15_PIO0 Data */
65 writew(0x2000, &sc520_mmcr->piodata31_16); /* PIO31_PIO16 Data */
66 writew(0x2000, &sc520_mmcr->piodir31_16); /* GPIO Direction */
67 writew(0x87b5, &sc520_mmcr->piodir15_0); /* GPIO Direction */
68 writew(0x0dfe, &sc520_mmcr->piopfs31_16); /* GPIO pin function 31-16 reg */
69 writew(0x200a, &sc520_mmcr->piopfs15_0); /* GPIO pin function 15-0 reg */
70 writeb(0xf8, &sc520_mmcr->cspfs); /* Chip Select Pin Function Select */
72 writel(0x200713f8, &sc520_mmcr->par[2]); /* Uart A (GPCS0, 0x013f8, 8 Bytes) */
73 writel(0x2c0712f8, &sc520_mmcr->par[3]); /* Uart B (GPCS3, 0x012f8, 8 Bytes) */
74 writel(0x300711f8, &sc520_mmcr->par[4]); /* Uart C (GPCS4, 0x011f8, 8 Bytes) */
75 writel(0x340710f8, &sc520_mmcr->par[5]); /* Uart D (GPCS5, 0x010f8, 8 Bytes) */
76 writel(0xe3ffc000, &sc520_mmcr->par[6]); /* SDRAM (0x00000000, 128MB) */
77 writel(0xaa3fd000, &sc520_mmcr->par[7]); /* StrataFlash (ROMCS1, 0x10000000, 16MB) */
78 writel(0xca3fd100, &sc520_mmcr->par[8]); /* StrataFlash (ROMCS2, 0x11000000, 16MB) */
79 writel(0x4203d900, &sc520_mmcr->par[9]); /* SRAM (GPCS0, 0x19000000, 1MB) */
80 writel(0x4e03d910, &sc520_mmcr->par[10]); /* SRAM (GPCS3, 0x19100000, 1MB) */
81 writel(0x50018100, &sc520_mmcr->par[11]); /* DP-RAM (GPCS4, 0x18100000, 4kB) */
82 writel(0x54020000, &sc520_mmcr->par[12]); /* CFLASH1 (0x200000000, 4kB) */
83 writel(0x5c020001, &sc520_mmcr->par[13]); /* CFLASH2 (0x200010000, 4kB) */
84 /* writel(0x8bfff800, &sc520_mmcr->par14); */ /* BOOTCS at 0x18000000 */
85 /* writel(0x38201000, &sc520_mmcr->par15); */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */
87 /* Disable Watchdog */
88 writew(0x3333, &sc520_mmcr->wdtmrctl);
89 writew(0xcccc, &sc520_mmcr->wdtmrctl);
90 writew(0x0000, &sc520_mmcr->wdtmrctl);
92 /* Chip Select Configuration */
93 writew(0x0033, &sc520_mmcr->bootcsctl);
94 writew(0x0615, &sc520_mmcr->romcs1ctl);
95 writew(0x0615, &sc520_mmcr->romcs2ctl);
98 * Set the timer pin mapping
99 * no clock frequency selected, use 1.1892MHz
101 writeb(0x72, &sc520_mmcr->clksel);
103 writeb(0x00, &sc520_mmcr->adddecctl);
104 writeb(0x07, &sc520_mmcr->uart1ctl);
105 writeb(0x07, &sc520_mmcr->uart2ctl);
106 writeb(0x06, &sc520_mmcr->sysarbctl);
107 writew(0x0003, &sc520_mmcr->sysarbmenb);
109 /* enable posted-writes */
110 writeb(0x04, &sc520_mmcr->hbctl);
115 int board_early_init_r(void)
117 /* CPU Speed to 100MHz */
118 gd->cpu_clk = 100000000;
120 /* Crystal is 33.000MHz */
121 gd->bus_clk = 33000000;
132 void show_boot_progress(int val)
139 led_mask |= LED_ERR_BITMASK;
141 led_mask |= (uchar)(val & 0x001f);
142 outb(led_mask, LED_LATCH_ADDRESS);
146 int last_stage_init(void)
153 outb(0x00, LED_LATCH_ADDRESS);
155 register_timer_isr (enet_timer_isr);
157 printf("Serck Controls eNET\n");
162 ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
164 if (banknum == 0) { /* non-CFI boot flash */
165 info->portwidth = FLASH_CFI_8BIT;
166 info->chipwidth = FLASH_CFI_BY8;
167 info->interface = FLASH_CFI_X8;
173 int board_eth_init(bd_t *bis)
175 return pci_eth_init(bis);
178 void setup_pcat_compatibility()
180 /* disable global interrupt mode */
181 writeb(0x40, &sc520_mmcr->picicr);
183 /* set all irqs to edge */
184 writeb(0x00, &sc520_mmcr->pic_mode[0]);
185 writeb(0x00, &sc520_mmcr->pic_mode[1]);
186 writeb(0x00, &sc520_mmcr->pic_mode[2]);
189 * active low polarity on PIC interrupt pins,
190 * active high polarity on all other irq pins
192 writew(0x0000,&sc520_mmcr->intpinpol);
201 writeb(SC520_IRQ0, &sc520_mmcr->pit_int_map[0]);
202 writeb(SC520_IRQ8, &sc520_mmcr->rtcmap);
203 writeb(SC520_IRQ13, &sc520_mmcr->ferrmap);
204 writeb(SC520_IRQ4, &sc520_mmcr->uart_int_map[0]);
205 writeb(SC520_IRQ3, &sc520_mmcr->uart_int_map[1]);
207 /* Disable all other interrupt sources */
208 writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[0]);
209 writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[1]);
210 writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[2]);
211 writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[1]);
212 writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[2]);
213 writeb(SC520_IRQ_DISABLED, &sc520_mmcr->ssimap);
214 writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wdtmap);
215 writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wpvmap);
216 writeb(SC520_IRQ_DISABLED, &sc520_mmcr->icemap);
219 void enet_timer_isr(void)
221 static long enet_ticks = 0;
225 /* Toggle Watchdog every 100ms */
226 if ((enet_ticks % 100) == 0)
229 /* Toggle Run LED every 500ms */
230 if ((enet_ticks % 500) == 0)
231 enet_toggle_run_led();
234 void hw_watchdog_reset(void)
236 /* Watchdog Reset must be atomic */
237 long flag = disable_interrupts();
239 if (sc520_mmcr->piodata15_0 & WATCHDOG_PIO_BIT)
240 sc520_mmcr->pioclr15_0 = WATCHDOG_PIO_BIT;
242 sc520_mmcr->pioset15_0 = WATCHDOG_PIO_BIT;
248 void enet_toggle_run_led(void)
250 unsigned char leds_state= inb(LED_LATCH_ADDRESS);
251 if (leds_state & LED_RUN_BITMASK)
252 outb(leds_state &~ LED_RUN_BITMASK, LED_LATCH_ADDRESS);
254 outb(leds_state | LED_RUN_BITMASK, LED_LATCH_ADDRESS);