3 * egnite GmbH <info@egnite.de>
6 * Ole Reinhardt <ole.reinhardt@thermotemp.de>
8 * SPDX-License-Identifier: GPL-2.0+
12 * Ethernut 5 general board support
14 * Ethernut is an open source hardware and software project for
15 * embedded Ethernet devices. Hardware layouts and CAD files are
16 * freely available under BSD-like license.
18 * Ethernut 5 is the first member of the Ethernut board family
19 * with U-Boot and Linux support. This implementation is based
20 * on the original work done by Ole Reinhardt, but heavily modified
21 * to support additional features and the latest board revision 5.0F.
23 * Main board components are by default:
25 * Atmel AT91SAM9XE512 CPU with 512 kBytes NOR Flash
26 * 2 x 64 MBytes Micron MT48LC32M16A2P SDRAM
27 * 512 MBytes Micron MT29F4G08ABADA NAND Flash
28 * 4 MBytes Atmel AT45DB321D DataFlash
29 * SMSC LAN8710 Ethernet PHY
30 * Atmel ATmega168 MCU used for power management
31 * Linear Technology LTC4411 PoE controller
33 * U-Boot relevant board interfaces are:
35 * 100 Mbit Ethernet with IEEE 802.3af PoE
39 * Expansion port with I2C, SPI and more...
41 * Typically the U-Boot image is loaded from serial DataFlash into
42 * SDRAM by the samboot boot loader, which is located in internal
43 * NOR Flash and provides all essential initializations like CPU
44 * and peripheral clocks and, of course, the SDRAM configuration.
46 * For testing purposes it is also possibly to directly transfer
47 * the image into SDRAM via JTAG. A tested configuration exists
48 * for the Turtelizer 2 hardware dongle and the OpenOCD software.
49 * In this case the latter will do the basic hardware configuration
50 * via its reset-init script.
52 * For additional information visit the project home page at
53 * http://www.ethernut.de/
62 #include <dataflash.h>
64 #include <atmel_mci.h>
66 #include <asm/arch/at91sam9260.h>
67 #include <asm/arch/at91sam9260_matrix.h>
68 #include <asm/arch/at91sam9_smc.h>
69 #include <asm/arch/at91_common.h>
70 #include <asm/arch/at91_pmc.h>
71 #include <asm/arch/at91_spi.h>
72 #include <asm/arch/gpio.h>
76 #include "ethernut5_pwrman.h"
78 DECLARE_GLOBAL_DATA_PTR;
80 AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
82 struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
83 {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}
87 * In fact we have 7 partitions, but u-boot supports 5 only. This is
88 * no big deal, because the first partition is reserved for applications
89 * and the last one is used by Nut/OS. Both need not to be visible here.
91 dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
92 { 0x00021000, 0x00041FFF, FLAG_PROTECT_SET, 0, "setup" },
93 { 0x00042000, 0x000C5FFF, FLAG_PROTECT_SET, 0, "uboot" },
94 { 0x000C6000, 0x00359FFF, FLAG_PROTECT_SET, 0, "kernel" },
95 { 0x0035A000, 0x003DDFFF, FLAG_PROTECT_SET, 0, "nutos" },
96 { 0x003DE000, 0x003FEFFF, FLAG_PROTECT_CLEAR, 0, "env" }
100 * This is called last during early initialization. Most of the basic
101 * hardware interfaces are up and running.
103 * The SDRAM hardware has been configured by the first stage boot loader.
104 * We only need to announce its size, using u-boot's memory check.
108 gd->ram_size = get_ram_size(
109 (void *)CONFIG_SYS_SDRAM_BASE,
110 CONFIG_SYS_SDRAM_SIZE);
114 #ifdef CONFIG_CMD_NAND
115 static void ethernut5_nand_hw_init(void)
117 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
118 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
121 /* Assign CS3 to NAND/SmartMedia Interface */
122 csa = readl(&matrix->ebicsa);
123 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
124 writel(csa, &matrix->ebicsa);
126 /* Configure SMC CS3 for NAND/SmartMedia */
127 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
128 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
130 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
131 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
133 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
135 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
136 AT91_SMC_MODE_EXNW_DISABLE |
137 AT91_SMC_MODE_DBW_8 |
138 AT91_SMC_MODE_TDF_CYCLE(2),
141 #ifdef CONFIG_SYS_NAND_READY_PIN
142 /* Ready pin is optional. */
143 at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
145 gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
150 * This is called first during late initialization.
154 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
156 /* Enable clocks for all PIOs */
157 writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
158 (1 << ATMEL_ID_PIOC),
160 /* Set adress of boot parameters. */
161 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
162 /* Initialize UARTs and power management. */
163 at91_seriald_hw_init();
164 ethernut5_power_init();
165 #ifdef CONFIG_CMD_NAND
166 ethernut5_nand_hw_init();
168 #ifdef CONFIG_HAS_DATAFLASH
169 at91_spi0_hw_init(1 << 0);
176 * This is optionally called last during late initialization.
178 int board_eth_init(bd_t *bis)
182 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
184 /* Enable on-chip EMAC clock. */
185 writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
186 /* Need to reset PHY via power management. */
187 ethernut5_phy_reset();
188 /* Set peripheral pins. */
190 /* Basic EMAC initialization. */
191 if (macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, CONFIG_PHY_ID))
194 * Early board revisions have a pull-down at the PHY's MODE0
195 * strap pin, which forces the PHY into power down. Here we
196 * switch to all-capable mode.
198 devname = miiphy_get_current_dev();
199 if (miiphy_read(devname, 0, 18, &mode) == 0) {
200 /* Set mode[2:0] to 0b111. */
202 miiphy_write(devname, 0, 18, mode);
203 /* Soft reset overrides strap pins. */
204 miiphy_write(devname, 0, MII_BMCR, BMCR_RESET);
206 /* Sync environment with network devices, needed for nfsroot. */
211 #ifdef CONFIG_GENERIC_ATMEL_MCI
212 int board_mmc_init(bd_t *bd)
214 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
216 /* Enable MCI clock. */
217 writel(1 << ATMEL_ID_MCI, &pmc->pcer);
218 /* Initialize MCI hardware. */
220 /* Register the device. */
221 return atmel_mci_init((void *)ATMEL_BASE_MCI);
224 int board_mmc_getcd(struct mmc *mmc)
226 return !at91_get_pio_value(CONFIG_SYS_MMC_CD_PIN);
230 #ifdef CONFIG_ATMEL_SPI
232 * Note, that u-boot uses different code for SPI bus access. While
233 * memory routines use automatic chip select control, the serial
234 * flash support requires 'manual' GPIO control. Thus, we switch
237 void spi_cs_activate(struct spi_slave *slave)
239 /* Enable NPCS0 in GPIO mode. This disables peripheral control. */
240 at91_set_pio_output(AT91_PIO_PORTA, 3, 0);
243 void spi_cs_deactivate(struct spi_slave *slave)
245 /* Disable NPCS0 in GPIO mode. */
246 at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
247 /* Switch back to peripheral chip select control. */
248 at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
251 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
253 return bus == 0 && cs == 0;