3 * egnite GmbH <info@egnite.de>
6 * Ole Reinhardt <ole.reinhardt@thermotemp.de>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * Ethernut 5 general board support
30 * Ethernut is an open source hardware and software project for
31 * embedded Ethernet devices. Hardware layouts and CAD files are
32 * freely available under BSD-like license.
34 * Ethernut 5 is the first member of the Ethernut board family
35 * with U-Boot and Linux support. This implementation is based
36 * on the original work done by Ole Reinhardt, but heavily modified
37 * to support additional features and the latest board revision 5.0F.
39 * Main board components are by default:
41 * Atmel AT91SAM9XE512 CPU with 512 kBytes NOR Flash
42 * 2 x 64 MBytes Micron MT48LC32M16A2P SDRAM
43 * 512 MBytes Micron MT29F4G08ABADA NAND Flash
44 * 4 MBytes Atmel AT45DB321D DataFlash
45 * SMSC LAN8710 Ethernet PHY
46 * Atmel ATmega168 MCU used for power management
47 * Linear Technology LTC4411 PoE controller
49 * U-Boot relevant board interfaces are:
51 * 100 Mbit Ethernet with IEEE 802.3af PoE
55 * Expansion port with I2C, SPI and more...
57 * Typically the U-Boot image is loaded from serial DataFlash into
58 * SDRAM by the samboot boot loader, which is located in internal
59 * NOR Flash and provides all essential initializations like CPU
60 * and peripheral clocks and, of course, the SDRAM configuration.
62 * For testing purposes it is also possibly to directly transfer
63 * the image into SDRAM via JTAG. A tested configuration exists
64 * for the Turtelizer 2 hardware dongle and the OpenOCD software.
65 * In this case the latter will do the basic hardware configuration
66 * via its reset-init script.
68 * For additional information visit the project home page at
69 * http://www.ethernut.de/
78 #include <dataflash.h>
80 #include <atmel_mci.h>
82 #include <asm/arch/at91sam9260.h>
83 #include <asm/arch/at91sam9260_matrix.h>
84 #include <asm/arch/at91sam9_smc.h>
85 #include <asm/arch/at91_common.h>
86 #include <asm/arch/at91_pmc.h>
87 #include <asm/arch/at91_spi.h>
88 #include <asm/arch/gpio.h>
91 #include "ethernut5_pwrman.h"
93 DECLARE_GLOBAL_DATA_PTR;
95 AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
97 struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
98 {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}
102 * In fact we have 7 partitions, but u-boot supports 5 only. This is
103 * no big deal, because the first partition is reserved for applications
104 * and the last one is used by Nut/OS. Both need not to be visible here.
106 dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
107 { 0x00021000, 0x00041FFF, FLAG_PROTECT_SET, 0, "setup" },
108 { 0x00042000, 0x000C5FFF, FLAG_PROTECT_SET, 0, "uboot" },
109 { 0x000C6000, 0x00359FFF, FLAG_PROTECT_SET, 0, "kernel" },
110 { 0x0035A000, 0x003DDFFF, FLAG_PROTECT_SET, 0, "nutos" },
111 { 0x003DE000, 0x003FEFFF, FLAG_PROTECT_CLEAR, 0, "env" }
115 * This is called last during early initialization. Most of the basic
116 * hardware interfaces are up and running.
118 * The SDRAM hardware has been configured by the first stage boot loader.
119 * We only need to announce its size, using u-boot's memory check.
123 gd->ram_size = get_ram_size(
124 (void *)CONFIG_SYS_SDRAM_BASE,
125 CONFIG_SYS_SDRAM_SIZE);
129 #ifdef CONFIG_CMD_NAND
130 static void ethernut5_nand_hw_init(void)
132 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
133 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
136 /* Assign CS3 to NAND/SmartMedia Interface */
137 csa = readl(&matrix->ebicsa);
138 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
139 writel(csa, &matrix->ebicsa);
141 /* Configure SMC CS3 for NAND/SmartMedia */
142 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
143 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
145 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
146 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
148 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
150 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
151 AT91_SMC_MODE_EXNW_DISABLE |
152 AT91_SMC_MODE_DBW_8 |
153 AT91_SMC_MODE_TDF_CYCLE(2),
156 #ifdef CONFIG_SYS_NAND_READY_PIN
157 /* Ready pin is optional. */
158 at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
160 at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
165 * This is called first during late initialization.
169 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
171 /* Enable clocks for all PIOs */
172 writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
173 (1 << ATMEL_ID_PIOC),
175 /* Set adress of boot parameters. */
176 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
177 /* Initialize UARTs and power management. */
178 at91_seriald_hw_init();
179 ethernut5_power_init();
180 #ifdef CONFIG_CMD_NAND
181 ethernut5_nand_hw_init();
183 #ifdef CONFIG_HAS_DATAFLASH
184 at91_spi0_hw_init(1 << 0);
191 * This is optionally called last during late initialization.
193 int board_eth_init(bd_t *bis)
197 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
199 /* Enable on-chip EMAC clock. */
200 writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
201 /* Need to reset PHY via power management. */
202 ethernut5_phy_reset();
203 /* Set peripheral pins. */
205 /* Basic EMAC initialization. */
206 if (macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, CONFIG_PHY_ID))
209 * Early board revisions have a pull-down at the PHY's MODE0
210 * strap pin, which forces the PHY into power down. Here we
211 * switch to all-capable mode.
213 devname = miiphy_get_current_dev();
214 if (miiphy_read(devname, 0, 18, &mode) == 0) {
215 /* Set mode[2:0] to 0b111. */
217 miiphy_write(devname, 0, 18, mode);
218 /* Soft reset overrides strap pins. */
219 miiphy_write(devname, 0, MII_BMCR, BMCR_RESET);
221 /* Sync environment with network devices, needed for nfsroot. */
222 return eth_init(gd->bd);
226 #ifdef CONFIG_GENERIC_ATMEL_MCI
227 int board_mmc_init(bd_t *bd)
229 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
231 /* Enable MCI clock. */
232 writel(1 << ATMEL_ID_MCI, &pmc->pcer);
233 /* Initialize MCI hardware. */
235 /* Register the device. */
236 return atmel_mci_init((void *)ATMEL_BASE_MCI);
239 int board_mmc_getcd(struct mmc *mmc)
241 return !at91_get_pio_value(CONFIG_SYS_MMC_CD_PIN);
245 #ifdef CONFIG_ATMEL_SPI
247 * Note, that u-boot uses different code for SPI bus access. While
248 * memory routines use automatic chip select control, the serial
249 * flash support requires 'manual' GPIO control. Thus, we switch
252 void spi_cs_activate(struct spi_slave *slave)
254 /* Enable NPCS0 in GPIO mode. This disables peripheral control. */
255 at91_set_pio_output(AT91_PIO_PORTA, 3, 0);
258 void spi_cs_deactivate(struct spi_slave *slave)
260 /* Disable NPCS0 in GPIO mode. */
261 at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
262 /* Switch back to peripheral chip select control. */
263 at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
266 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
268 return bus == 0 && cs == 0;