2 * (C) Copyright 2001 ELTEC Elektronik AG
3 * Frank Gottschling <fgottschling@eltec.de>
5 * ELTEC BAB PPC RAM initialization
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/processor.h>
32 #include <ppc_asm.tmpl>
36 * This following contains the entry code for the initialization code
37 * for the MPC 106, a PCI Bridge/Memory Controller.
39 * r0 = ramtest scratch register, toggleError loop counter
40 * r1 = 0xfec0 0cf8 CONFIG_ADDRESS
41 * r2 = 0xfee0 0cfc CONFIG_DATA
42 * r3 = scratch register, subroutine argument and return value, ramtest size
43 * r4 = scratch register, spdRead clock mask, OutHex loop count
44 * r5 = ramtest scratch register
45 * r6 = toggleError 1st value, spdRead port mask
46 * r7 = toggleError 2nd value, ramtest scratch register,
47 * spdRead scratch register (0x00)
48 * r8 = ramtest scratch register, spdRead scratch register (0x80)
49 * r9 = ramtest scratch register, toggleError loop end, OutHex digit
50 * r10 = ramtest scratch register, spdWriteByte parameter,
51 * spdReadByte return value, printf pointer to COM1
53 * r12 = ramtest scratch register, spdRead data mask
54 * r13 = pointer to message block
55 * r14 = pointer to GOT
56 * r15 = scratch register, SPD save
57 * r16 = bank0 size, total memory size
66 * r25 = save link register 1st level
67 * r26 = save link register 2nd level
68 * r27 = save link register 3rd level
69 * r30 = pointer to GPIO for spdRead
76 * setup pointer to message block
78 mflr r25 /* save away link register */
79 bl get_lnk_reg /* r3=addr of next instruction */
80 subi r4, r3, 8 /* r4=board_asm_init addr */
81 addi r13, r4, (MessageBlock-board_asm_init)
107 ori r3, r3, (HID0_ICE | HID0_ICFI | HID0_DCI | HID0_DCE)
119 ori r3, r3, (HID0_ICE | HID0_ICFI)
128 #ifdef CONFIG_SYS_ADDRESS_MAP_A
130 * Switch to address map A if necessary.
133 ori r3, r3, PCI_PICR1
138 lis r0, PICR1_XIO_MODE@h
139 ori r0, r0, PICR1_XIO_MODE@l
141 lis r0, PICR1_ADDRESS_MAP@h
142 ori r0, r0, PICR1_ADDRESS_MAP@l
149 * Do the init for the SIO.
153 addi r3, r13, (MinitLogo-MessageBlock)
156 addi r3, r13, (Mspd01-MessageBlock)
159 * Memory cofiguration using SPD information stored on the SODIMMs
165 li r3, 0x0002 /* get RAM type from spd for bank0/1 */
168 cmpi 0, 0, r3, -1 /* error ? */
171 addi r3, r13, (Mfail-MessageBlock)
174 li r6, 0xe0 /* error codes in r6 and r7 */
176 b toggleError /* fail - loop forever */
179 mr r15, r3 /* save r3 */
181 addi r3, r13, (Mok-MessageBlock)
184 cmpli 0, 0, r15, 0x0001 /* FPM ? */
186 cmpli 0, 0, r15, 0x0002 /* EDO ? */
188 cmpli 0, 0, r15, 0x0004 /* SDRAM ? */
191 li r6, 0xe0 /* error codes in r6 and r7 */
193 b toggleError /* fail - loop forever */
196 addi r3, r13, (MsdRam-MessageBlock)
199 * set the Memory Configuration Reg. 1
201 li r3, 0x001f /* get bank size from spd bank0/1 */
207 li r3, 0x0011 /* get number of internal banks */
208 /* from spd for bank0/1 */
217 li r6, 0xe0 /* error codes in r6 and r7 */
219 b toggleError /* fail - loop forever */
222 li r20, 0x0005 /* 64-Mbit SDRAM 2 banks */
226 li r20, 0x0000 /* 64-Mbit SDRAM 4 banks */
230 li r20, 0x000f /* 16-Mbit SDRAM 2 banks */
233 li r3, 0x0102 /* get RAM type spd for bank2/3 */
236 cmpli 0, 0, r3, 0x0004
237 bne S2D64MB4B /* bank2/3 isn't present or no SDRAM */
239 li r3, 0x011f /* get bank size from spd bank2/3 */
245 * set the Memory Configuration Reg. 2
247 li r3, 0x0111 /* get number of internal banks */
248 /* from spd for bank2/3 */
257 li r6, 0xe0 /* error codes in r6 and r7 */
259 b toggleError /* fail - loop forever */
262 ori r20, r20, 0x0050 /* 64-Mbit SDRAM 2 banks */
266 ori r20, r20, 0x00f0 /* 16-Mbit SDRAM 2 banks */
269 * set the Memory Configuration Reg. 3
272 lis r21, 0x8630 /* BSTOPRE = 0x80, REFREC = 6, */
276 * set the Memory Configuration Reg. 4
278 lis r22, 0x2430 /* PRETOACT = 2, ACTOPRE = 4, */
279 /* WCBUF = 1, RCBUF = 1 */
280 ori r22, r22, 0x2220 /* SDMODE = 0x022, ACTORW = 2 */
283 * get the size of bank 0-3
285 li r3, 0x001f /* get bank size from spd bank0/1 */
288 rlwinm r16, r3, 2, 24, 29 /* calculate size in MByte */
291 li r3, 0x0005 /* get number of banks from spd */
295 cmpi 0, 0, r3, 2 /* 2 banks ? */
301 addi r3, r13, (Mspd23-MessageBlock)
304 li r3, 0x0102 /* get RAM type spd for bank2/3 */
307 cmpli 0, 0, r3, 0x0001 /* FPM ? */
308 bne noFPM23 /* handle as EDO */
309 addi r3, r13, (Mok-MessageBlock)
311 addi r3, r13, (MfpmRam-MessageBlock)
315 cmpli 0, 0, r3, 0x0002 /* EDO ? */
317 addi r3, r13, (Mok-MessageBlock)
319 addi r3, r13, (MedoRam-MessageBlock)
323 cmpli 0, 0, r3, 0x0004 /* SDRAM ? */
325 addi r3, r13, (Mok-MessageBlock)
327 addi r3, r13, (MsdRam-MessageBlock)
331 addi r3, r13, (Mna-MessageBlock)
333 b configRAMcommon /* bank2/3 isn't present or no SDRAM */
336 li r3, 0x011f /* get bank size from spd bank2/3 */
339 rlwinm r18, r3, 2, 24, 29 /* calculate size in MByte */
342 li r3, 0x0105 /* get number of banks from */
346 cmpi 0, 0, r3, 2 /* 2 banks ? */
355 addi r3, r13, (MfpmRam-MessageBlock)
359 * set the Memory Configuration Reg. 1
362 addi r3, r13, (MedoRam-MessageBlock)
365 lis r20, MCCR1_TYPE_EDO@h
368 li r3, 0x0003 /* get number of row bits from */
369 /* spd from bank0/1 */
371 ori r20, r20, (MCCR1_BK0_9BITS | MCCR1_BK1_9BITS)
372 cmpli 0, 0, r3, 0x0009 /* bank0 - 9 row bits */
375 ori r20, r20, (MCCR1_BK0_10BITS | MCCR1_BK1_10BITS)
376 cmpli 0, 0, r3, 0x000a /* bank0 - 10 row bits */
379 ori r20, r20, (MCCR1_BK0_11BITS | MCCR1_BK1_11BITS)
380 cmpli 0, 0, r3, 0x000b /* bank0 - 11 row bits */
383 ori r20, r20, (MCCR1_BK0_12BITS | MCCR1_BK1_12BITS)
384 cmpli 0, 0, r3, 0x000c /* bank0 - 12 row bits */
387 cmpli 0, 0, r3, 0x000d /* bank0 - 13 row bits */
390 li r6, 0xe0 /* error codes in r6 and r7 */
392 b toggleError /* fail - loop forever */
395 li r3, 0x0103 /* get number of row bits from */
396 /* spd for bank2/3 */
399 ori r20, r20, (MCCR1_BK2_9BITS | MCCR1_BK3_9BITS)
400 cmpli 0, 0, r3, 0x0009 /* bank0 - 9 row bits */
403 ori r20, r20, (MCCR1_BK2_10BITS | MCCR1_BK3_10BITS)
404 cmpli 0, 0, r3, 0x000a /* bank0 - 10 row bits */
407 ori r20, r20, (MCCR1_BK2_11BITS | MCCR1_BK3_11BITS)
408 cmpli 0, 0, r3, 0x000b /* bank0 - 11 row bits */
411 ori r20, r20, (MCCR1_BK2_12BITS | MCCR1_BK3_12BITS)
414 * set the Memory Configuration Reg. 3
417 lis r21, 0x000a /* CPX = 1, RAS6P = 4 */
418 ori r21, r21, 0x2293 /* CAS5 = 2, CP4 = 1, */
419 /* CAS3 = 2, RCD2 = 2, RP = 3 */
421 * set the Memory Configuration Reg. 4
423 lis r22, 0x0010 /* all SDRAM parameter 0, */
424 /* WCBUF flow through, */
425 /* RCBUF registered */
427 * get the size of bank 0-3
429 li r3, 0x0003 /* get row bits from spd bank0/1 */
432 li r16, 0 /* bank size is: */
433 /* (8*2^row*2^column)/0x100000 MB */
435 rlwnm r16, r16, r3, 0, 31
437 li r3, 0x0004 /* get column bits from spd bank0/1 */
440 rlwnm r16, r16, r3, 0, 31
442 li r3, 0x0005 /* get number of banks from */
443 /* spd for bank0/1 */
446 cmpi 0, 0, r3, 2 /* 2 banks ? */
452 addi r3, r13, (Mspd23-MessageBlock)
455 li r3, 0x0102 /* get RAM type spd for bank2/3 */
458 cmpli 0, 0, r3, 0x0001 /* FPM ? */
459 bne noFPM231 /* handle as EDO */
460 addi r3, r13, (Mok-MessageBlock)
462 addi r3, r13, (MfpmRam-MessageBlock)
466 cmpli 0, 0, r3, 0x0002 /* EDO ? */
468 addi r3, r13, (Mok-MessageBlock)
470 addi r3, r13, (MedoRam-MessageBlock)
474 cmpli 0, 0, r3, 0x0004 /* SDRAM ? */
476 addi r3, r13, (Mok-MessageBlock)
478 addi r3, r13, (MsdRam-MessageBlock)
482 addi r3, r13, (Mfail-MessageBlock)
484 b configRAMcommon /* bank2/3 isn't present or no SDRAM */
487 li r3, 0x0103 /* get row bits from spd for bank2/3 */
490 li r18, 0 /* bank size is: */
491 /* (8*2^row*2^column)/0x100000 MB */
493 rlwnm r18, r18, r3, 0, 31
495 li r3, 0x0104 /* get column bits from spd bank2/3 */
498 rlwnm r18, r18, r3, 0, 31
500 li r3, 0x0105 /* get number of banks from */
501 /* spd for bank2/3 */
504 cmpi 0, 0, r3, 2 /* 2 banks ? */
510 lis r1, MPC106_REG_ADDR@h
511 ori r1, r1, MPC106_REG_ADDR@l
512 lis r2, MPC106_REG_DATA@h
513 ori r2, r2, MPC106_REG_DATA@l
518 * If we are already running in RAM (debug mode), we should
519 * NOT reset the MEMGO flag. Otherwise we will stop all memory
523 lis r4, MCCR1_MEMGO@h
524 ori r4, r4, MCCR1_MEMGO@l
529 * set the Memory Configuration Reg. 1
531 lis r3, MPC106_REG@h /* start building new reg number */
532 ori r3, r3, MPC106_MCCR1 /* register number 0xf0 */
533 stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */
534 eieio /* make sure mem. access is complete */
535 stwbrx r20, r0, r2 /* write data to CONFIG_DATA */
537 * set the Memory Configuration Reg. 3
539 lis r3, MPC106_REG@h /* start building new reg number */
540 ori r3, r3, MPC106_MCCR3 /* register number 0xf8 */
541 stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */
542 eieio /* make sure mem. access is complete */
543 stwbrx r21, r0, r2 /* write data to CONFIG_DATA */
545 * set the Memory Configuration Reg. 4
547 lis r3, MPC106_REG@h /* start building new reg number */
548 ori r3, r3, MPC106_MCCR4 /* register number 0xfc */
549 stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */
550 eieio /* make sure mem. access is complete */
551 stwbrx r22, r0, r2 /* write data to CONFIG_DATA */
553 * set the memory boundary registers for bank 0-3
558 subi r21, r16, 1 /* calculate end address bank0 */
561 cmpi 0, 0, r17, 0 /* bank1 present ? */
564 rlwinm r3, r16, 8, 16, 23 /* calculate start address of bank1 */
566 add r16, r16, r17 /* add to total memory size */
567 subi r3, r16, 1 /* calculate end address of bank1 */
568 rlwinm r3, r3, 8, 16, 23
570 ori r22, r22, (MBER_BANK1) /* enable bank1 */
574 ori r23, r23, 0x0300 /* set bank1 start to unused area */
575 ori r24, r24, 0x0300 /* set bank1 end to unused area */
578 cmpi 0, 0, r18, 0 /* bank2 present ? */
581 andi. r3, r16, 0x00ff /* calculate start address of bank2 */
582 andi. r4, r16, 0x0300
583 rlwinm r3, r3, 16, 8, 15
585 rlwinm r3, r4, 8, 8, 15
587 add r16, r16, r18 /* add to total memory size */
588 subi r3, r16, 1 /* calculate end address of bank2 */
591 rlwinm r3, r3, 16, 8, 15
593 rlwinm r3, r4, 8, 8, 15
595 ori r22, r22, (MBER_BANK2) /* enable bank2 */
600 or r23, r23, r3 /* set bank2 start to unused area */
601 or r24, r24, r3 /* set bank2 end to unused area */
604 cmpi 0, 0, r19, 0 /* bank3 present ? */
607 andi. r3, r16, 0x00ff /* calculate start address of bank3 */
608 andi. r4, r16, 0x0300
609 rlwinm r3, r3, 24, 0, 7
611 rlwinm r3, r4, 16, 0, 7
613 add r16, r16, r19 /* add to total memory size */
614 subi r3, r16, 1 /* calculate end address of bank3 */
617 rlwinm r3, r3, 24, 0, 7
619 rlwinm r3, r4, 16, 0, 7
621 ori r22, r22, (MBER_BANK3) /* enable bank3 */
626 or r23, r23, r3 /* set bank3 start to unused area */
627 or r24, r24, r3 /* set bank3 end to unused area */
630 lis r3, MPC106_REG@h /* start building new reg number */
631 ori r3, r3, MPC106_MSAR1 /* register number 0x80 */
632 stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */
633 eieio /* make sure mem. access is complete */
634 stwbrx r20, r0, r2 /* write data to CONFIG_DATA */
636 lis r3, MPC106_REG@h /* start building new reg number */
637 ori r3, r3, MPC106_MEAR1 /* register number 0x90 */
638 stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */
639 eieio /* make sure mem. access is complete */
640 stwbrx r21, r0, r2 /* write data to CONFIG_DATA */
642 lis r3, MPC106_REG@h /* start building new reg number */
643 ori r3, r3, MPC106_EMSAR1 /* register number 0x88 */
644 stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */
645 eieio /* make sure mem. access is complete */
646 stwbrx r23, r0, r2 /* write data to CONFIG_DATA */
648 lis r3, MPC106_REG@h /* start building new reg number */
649 ori r3, r3, MPC106_EMEAR1 /* register number 0x98 */
650 stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */
651 eieio /* make sure mem. access is complete */
652 stwbrx r24, r0, r2 /* write data to CONFIG_DATA */
655 * set boundaries of unused banks to unused address space
658 ori r4, r4, 0x0303 /* bank 4-7 start and end adresses */
659 lis r3, MPC106_REG@h /* start building new reg number */
660 ori r3, r3, MPC106_EMSAR2 /* register number 0x8C */
661 stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */
662 eieio /* make sure mem. access is complete */
663 stwbrx r4, r0, r2 /* write data to CONFIG_DATA */
665 lis r3, MPC106_REG@h /* start building new reg number */
666 ori r3, r3, MPC106_EMEAR2 /* register number 0x9C */
667 stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */
668 eieio /* make sure mem. access is complete */
669 stwbrx r4, r0, r2 /* write data to CONFIG_DATA */
672 * set the Memory Configuration Reg. 2
674 lis r3, MPC106_REG@h /* start building new reg number */
675 ori r3, r3, MPC106_MCCR2 /* register number 0xf4 */
676 stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */
677 eieio /* make sure mem. access is complete */
679 li r3, 0x000c /* get refresh from spd for bank0/1 */
682 cmpi 0, 0, r3, -1 /* error ? */
685 li r6, 0xe0 /* error codes in r6 and r7 */
687 b toggleError /* fail - loop forever */
690 andi. r15, r3, 0x007f /* mask selfrefresh bit */
691 li r3, 0x010c /* get refresh from spd for bank2/3 */
694 cmpi 0, 0, r3, -1 /* error ? */
696 andi. r3, r3, 0x007f /* mask selfrefresh bit */
697 cmp 0, 0, r3, r15 /* find the lower */
704 li r4, 0x1010 /* refesh cycle 1028 clocks */
706 cmpli 0, 0, r3, 0x0000 /* 15.6 us ? */
709 li r4, 0x0808 /* refesh cycle 514 clocks */
711 cmpli 0, 0, r3, 0x0002 /* 7.8 us ? */
714 li r4, 0x2020 /* refesh cycle 2056 clocks */
716 cmpli 0, 0, r3, 0x0003 /* 31.3 us ? */
719 li r4, 0x4040 /* refesh cycle 4112 clocks */
721 cmpli 0, 0, r3, 0x0004 /* 62.5 us ? */
725 ori r4, r4, 0x8080 /* refesh cycle 8224 clocks */
727 cmpli 0, 0, r3, 0x0005 /* 125 us ? */
730 li r6, 0xe0 /* error codes in r6 and r7 */
732 b toggleError /* fail - loop forever */
735 stwbrx r4, r0, r2 /* write data to CONFIG_DATA */
738 * DRAM BANKS SHOULD BE ENABLED
740 addi r3, r13, (Mactivate-MessageBlock)
744 addi r3, r13, (Mmbyte-MessageBlock)
747 lis r3, MPC106_REG@h /* start building new reg number */
748 ori r3, r3, MPC106_MBER /* register number 0xa0 */
749 stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */
750 eieio /* make sure mem. access is complete */
751 stb r22, 0(r2) /* write data to CONFIG_DATA */
752 li r8, 0x63 /* PGMAX = 99 */
753 stb r8, 3(r2) /* write data to CONFIG_DATA */
756 * DRAM SHOULD NOW BE CONFIGURED AND ENABLED
757 * MUST WAIT 200us BEFORE ACCESSING
765 lis r3, MPC106_REG@h /* start building new reg number */
766 ori r3, r3, MPC106_MCCR1 /* register number 0xf0 */
767 stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */
768 eieio /* make sure mem. access is complete */
770 lwbrx r4, r0, r2 /* load r4 from CONFIG_DATA */
772 lis r0, MCCR1_MEMGO@h /* MEMGO=1 */
773 ori r0, r0, MCCR1_MEMGO@l
774 or r4, r4, r0 /* set the MEMGO bit */
775 stwbrx r4, r0, r2 /* write mdfd data to CONFIG_DATA */
783 addi r3, r13, (Mok-MessageBlock)
790 * Infinite loop called in case of an error during RAM initialisation.
791 * error codes in r6 and r7.
800 ble cr1, toggleError1
807 ble cr1, toggleError2
811 /******************************************************************************
812 * This function performs a basic initialisation of the superio chip
813 * to enable basic console output and SPD access during RAM initialisation.
815 * Upon completion, SIO resource registers are mapped as follows:
816 * Resource Enabled Address
817 * UART1 Yes 3F8-3FF COM1
818 * UART2 Yes 2F8-2FF COM2
821 .set SIO_LUNINDEX, 0x07 /* SIO LUN index register */
822 .set SIO_CNFG1, 0x21 /* SIO configuration #1 register */
823 .set SIO_PCSCI, 0x23 /* SIO PCS configuration index reg */
824 .set SIO_PCSCD, 0x24 /* SIO PCS configuration data reg */
825 .set SIO_ACTIVATE, 0x30 /* SIO activate register */
826 .set SIO_IOBASEHI, 0x60 /* SIO I/O port base address, 15:8 */
827 .set SIO_IOBASELO, 0x61 /* SIO I/O port base address, 7:0 */
828 .set SIO_LUNENABLE, 0x01 /* SIO LUN enable */
831 mfspr r7, 8 /* save link register */
836 * Get base addr of ISA I/O space
838 lis r6, CONFIG_SYS_ISA_IO@h
839 ori r6, r6, CONFIG_SYS_ISA_IO@l
842 * Set offset to base address for config registers.
844 #if defined(CONFIG_SYS_NS87308_BADDR_0x)
846 #elif defined(CONFIG_SYS_NS87308_BADDR_10)
848 #elif defined(CONFIG_SYS_NS87308_BADDR_11)
851 add r6, r6, r4 /* add offset to base */
852 or r3, r6, r6 /* make a copy */
857 addi r4, r0, SIO_LUNINDEX /* select PMC LUN */
860 addi r4, r0, SIO_IOBASEHI /* initialize PMC address to 0x460 */
863 addi r4, r0, SIO_IOBASELO
866 addi r4, r0, SIO_ACTIVATE /* enable PMC */
867 addi r5, r0, SIO_LUNENABLE
870 lis r8, CONFIG_SYS_ISA_IO@h
873 stb r9, 0(r8) /* select PMC2 register */
876 stb r9, 1(r8) /* SuperI/O clock src: 24MHz via X1 */
880 * map UART1 (LUN 6) or UART2 (LUN 5) to COM1 (0x3F8)
882 addi r4, r0, SIO_LUNINDEX /* select COM1 LUN */
886 addi r4, r0, SIO_IOBASEHI /* initialize COM1 address to 0x3F8 */
890 addi r4, r0, SIO_IOBASELO
894 addi r4, r0, SIO_ACTIVATE /* enable COM1 */
895 addi r5, r0, SIO_LUNENABLE
899 * Init COM1 for polled output
901 lis r8, CONFIG_SYS_ISA_IO@h
904 stb r9, 1(r8) /* int disabled */
907 stb r9, 4(r8) /* modem ctrl */
910 stb r9, 3(r8) /* link ctrl, bank select */
912 li r9, 115200/CONFIG_BAUDRATE
913 stb r9, 0(r8) /* baud rate (LSB)*/
916 stb r9, 1(r8) /* baud rate (MSB) */
919 stb r9, 3(r8) /* 8 data bits, 1 stop bit, */
923 stb r9, 4(r8) /* enable the receiver and transmitter */
927 lbz r9, 5(r8) /* transmit empty */
931 stb r9, 3(r8) /* send break, 8 data bits, */
932 /* 2 stop bits, no parity */
939 lwz r0, 5(r8) /* load from port for delay */
943 lbz r9, 5(r8) /* transmit empty */
947 stb r9, 3(r8) /* 8 data bits, 2 stop bits, */
954 addi r4, r0, SIO_LUNINDEX /* select GPIO LUN */
958 addi r4, r0, SIO_IOBASEHI /* initialize GPIO address to 0x220 */
962 addi r4, r0, SIO_IOBASELO
966 addi r4, r0, SIO_ACTIVATE /* enable GPIO */
967 addi r5, r0, SIO_LUNENABLE
973 * Get base addr of ISA I/O space
975 lis r3, CONFIG_SYS_ISA_IO@h
976 ori r3, r3, CONFIG_SYS_ISA_IO@l
978 addi r3, r3, 0x015C /* adjust to superI/O 87308 base */
979 or r6, r3, r3 /* make a copy */
983 addi r4, r0, SIO_PCSCI /* select PCSCIR */
986 addi r4, r0, SIO_PCSCD /* select PCSCDR */
989 addi r4, r0, SIO_PCSCI /* select PCSCIR */
992 addi r4, r0, SIO_PCSCD /* select PCSCDR */
995 addi r4, r0, SIO_PCSCI /* select PCSCIR */
998 addi r4, r0, SIO_PCSCD /* select PCSCDR */
1004 addi r4, r0, SIO_PCSCI /* select PCSCIR */
1007 addi r4, r0, SIO_PCSCD /* select PCSCDR */
1010 addi r4, r0, SIO_PCSCI /* select PCSCIR */
1013 addi r4, r0, SIO_PCSCD /* select PCSCDR */
1016 addi r4, r0, SIO_PCSCI /* select PCSCIR */
1019 addi r4, r0, SIO_PCSCD /* select PCSCDR */
1025 addi r4, r0, SIO_PCSCI /* select PCSCIR */
1028 addi r4, r0, SIO_PCSCD /* select PCSCDR */
1031 addi r4, r0, SIO_PCSCI /* select PCSCIR */
1034 addi r4, r0, SIO_PCSCD /* select PCSCDR */
1037 addi r4, r0, SIO_PCSCI /* select PCSCIR */
1040 addi r4, r0, SIO_PCSCD /* select PCSCDR */
1044 mtspr 8, r7 /* restore link register */
1045 bclr 20, 0 /* return to caller */
1048 * this function writes a register to the SIO chip
1051 stb r4, 0(r3) /* write index register with register offset */
1054 stb r5, 1(r3) /* 1st write */
1057 stb r5, 1(r3) /* 2nd write */
1060 bclr 20, 0 /* return to caller */
1062 * this function reads a register from the SIO chip
1065 stb r4, 0(r3) /* write index register with register offset */
1068 lbz r3, 1(r3) /* retrieve specified reg offset contents */
1071 bclr 20, 0 /* return to caller */
1074 * Print a message to COM1 in polling mode
1075 * r10=COM1 port, r3=(char*)string
1079 lis r10, CONFIG_SYS_ISA_IO@h /* COM1 port */
1080 ori r10, r10, 0x03f8
1083 lbz r0, 5(r10) /* read link status */
1085 andi. r0, r0, 0x40 /* mask transmitter empty bit */
1086 beq cr0, WaitChr /* wait till empty */
1087 lbzx r0, r0, r3 /* get char */
1088 stb r0, 0(r10) /* write to transmit reg */
1090 addi r3, r3, 1 /* next char */
1091 lbzx r0, r0, r3 /* get char */
1092 cmpwi cr1, r0, 0 /* end of string ? */
1097 * Print 8/4/2 digits hex value to COM1 in polling mode
1098 * r10=COM1 port, r3=val
1101 li r9, 4 /* shift reg for 2 digits */
1104 li r9, 12 /* shift reg for 4 digits */
1108 li r9, 28 /* shift reg for 8 digits */
1110 lis r10, CONFIG_SYS_ISA_IO@h /* COM1 port */
1111 ori r10, r10, 0x03f8
1113 lbz r0, 5(r10) /* read link status */
1115 andi. r0, r0, 0x40 /* mask transmitter empty bit */
1126 stb r0, 0(r10) /* write to transmit reg */
1132 * Print 3 digits hdec value to COM1 in polling mode
1133 * r10=COM1 port, r3=val, r7=x00, r8=x0, r9=x, r0, r6=scratch
1138 divwu r0, r3, r6 /* r0 = r3 / 10, r9 = r3 mod 10 */
1143 divwu r0, r3, r6 /* r0 = r3 / 10, r8 = r3 mod 10 */
1148 divwu r0, r3, r6 /* r0 = r3 / 10, r7 = r3 mod 10 */
1152 lis r10, CONFIG_SYS_ISA_IO@h /* COM1 port */
1153 ori r10, r10, 0x03f8
1161 addi r3, r7, 48 /* convert to ASCII */
1164 lbz r0, 0(r13) /* slow down dummy read */
1165 lbz r0, 5(r10) /* read link status */
1167 andi. r0, r0, 0x40 /* mask transmitter empty bit */
1169 stb r3, 0(r10) /* x00 to transmit */
1175 addi r3, r8, 48 /* convert to ASCII */
1177 lbz r0, 0(r13) /* slow down dummy read */
1178 lbz r0, 5(r10) /* read link status */
1180 andi. r0, r0, 0x40 /* mask transmitter empty bit */
1182 stb r3, 0(r10) /* x0 to transmit */
1185 addi r3, r9, 48 /* convert to ASCII */
1187 lbz r0, 0(r13) /* slow down dummy read */
1188 lbz r0, 5(r10) /* read link status */
1190 andi. r0, r0, 0x40 /* mask transmitter empty bit */
1192 stb r3, 0(r10) /* x to transmit */
1196 * Print a char to COM1 in polling mode
1197 * r10=COM1 port, r3=char
1201 lis r10, CONFIG_SYS_ISA_IO@h /* COM1 port */
1202 ori r10, r10, 0x03f8
1205 lbz r0, 5(r10) /* read link status */
1207 andi. r0, r0, 0x40 /* mask transmitter empty bit */
1208 beq cr0, OutChr1 /* wait till empty */
1209 stb r3, 0(r10) /* write to transmit reg */
1213 * Input: r3 adr to read
1214 * Output: r3 val or -1 for error
1217 mfspr r26, 8 /* save link register */
1219 lis r30, CONFIG_SYS_ISA_IO@h
1220 ori r30, r30, 0x220 /* GPIO Port 1 */
1231 li r12, 0x20 /* set I2C data */
1232 li r4, 0x40 /* set I2C clock */
1233 li r6, 0x60 /* set I2C clock and data */
1238 bl spdStart /* access I2C bus as master */
1239 li r10, 0xa0 /* write to SPD */
1241 bl spdReadAck /* ACK returns in r10 */
1243 bne AckErr /* r10 must be 0, if ACK received */
1244 mr r10, r3 /* adr to read */
1250 li r10, 0xa1 /* read from SPD */
1255 bl spdReadByte /* return val in r10 */
1257 bl spdStop /* release I2C bus */
1259 mtspr 8, r26 /* restore link register */
1262 * ACK error occurred
1266 orc r3, r0, r0 /* return -1 */
1267 mtspr 8, r26 /* restore link register */
1271 * Routines to read from RAM spd.
1272 * r30 - GPIO Port1 address in all cases.
1273 * r4 - clock mask for SPD
1274 * r6 - port mask for SPD
1275 * r12 - data mask for SPD
1282 bclr 20, 0 /* return to caller */
1285 * establish START condition on I2C bus
1288 mfspr r27, 8 /* save link register */
1289 stb r6, 0(r30) /* set SDA and SCL */
1291 stb r6, 1(r30) /* switch GPIO to output */
1294 stb r4, 0(r30) /* reset SDA */
1297 stb r7, 0(r30) /* reset SCL */
1301 bclr 20, 0 /* return to caller */
1304 * establish STOP condition on I2C bus
1307 mfspr r27, 8 /* save link register */
1308 stb r7, 0(r30) /* reset SCL and SDA */
1310 stb r6, 1(r30) /* switch GPIO to output */
1313 stb r4, 0(r30) /* set SCL */
1316 stb r6, 0(r30) /* set SDA and SCL */
1319 stb r7, 1(r30) /* switch GPIO to input */
1322 bclr 20, 0 /* return to caller */
1326 stb r4, 1(r30) /* set GPIO for SCL output */
1331 stb r7, 0(r30) /* reset SDA and SCL */
1334 stb r4, 0(r30) /* set SCL */
1337 lbz r5, 0(r30) /* read from GPIO Port1 */
1338 rlwinm r10, r10, 1, 0, 31
1341 ori r10, r10, 0x01 /* append _1_ */
1343 stb r7, 0(r30) /* reset SCL */
1349 bclr 20, 0 /* return (r10) to caller */
1352 * spdWriteByte writes bits 24 - 31 of r10 to I2C.
1353 * r8 contains bit mask 0x80
1356 mfspr r27, 8 /* save link register */
1357 li r9, 0x08 /* write octet */
1360 stb r7, 0(r30) /* set SDA to _0_ */
1364 stb r12, 0(r30) /* set SDA to _1_ */
1367 stb r6, 1(r30) /* set GPIO to output */
1372 stb r7, 0(r30) /* set SDA to _0_ */
1376 stb r12, 0(r30) /* set SDA to _1_ */
1382 stb r4, 0(r30) /* set SDA to _0_ and SCL */
1386 stb r6, 0(r30) /* set SDA to _1_ and SCL */
1392 stb r7, 0(r30) /* set SDA to _0_ and reset SCL */
1396 stb r12, 0(r30) /* set SDA to _1_ and reset SCL */
1400 rlwinm r10, r10, 1, 0, 31 /* next bit */
1404 bclr 20, 0 /* return to caller */
1407 * Read ACK from SPD, return value in r10
1410 mfspr r27, 8 /* save link register */
1411 stb r4, 1(r30) /* set GPIO to output */
1413 stb r7, 0(r30) /* reset SDA and SCL */
1416 stb r4, 0(r30) /* set SCL */
1419 lbz r10, 0(r30) /* read GPIO Port 1 and mask SDA */
1422 stb r7, 0(r30) /* reset SDA and SCL */
1426 bclr 20, 0 /* return (r10) to caller */
1430 stb r12, 0(r30) /* set SCL */
1432 stb r6, 1(r30) /* set GPIO to output */
1435 stb r6, 0(r30) /* SDA and SCL */
1438 stb r12, 0(r30) /* reset SCL */
1442 bclr 20, 0 /* return to caller */
1445 mflr r3 /* return link reg */
1449 * Messages for console output
1454 .ascii "OK\015\012\000"
1456 .ascii "FAILED\015\012\000"
1458 .ascii "NA\015\012\000"
1460 .ascii "\015\012*** ELTEC Elektronik, Mainz ***\015\012"
1461 .ascii "\015\012Initialising RAM\015\012\000"
1463 .ascii " Reading SPD of bank0/1 ..... \000"
1465 .ascii " Reading SPD of bank2/3 ..... \000"
1467 .ascii " RAM-Type: FPM \015\012\000"
1469 .ascii " RAM-Type: EDO \015\012\000"
1471 .ascii " RAM-Type: SDRAM \015\012\000"
1473 .ascii " Activating \000"
1475 .ascii " MB .......... \000"