2 * Copyright (C) 2014 Eukréa Electromatique
3 * Author: Eric Bénard <eric@eukrea.com>
4 * Fabio Estevam <fabio.estevam@freescale.com>
5 * Jon Nettleton <jon.nettleton@gmail.com>
7 * based on sabresd.c which is :
8 * Copyright (C) 2012 Freescale Semiconductor, Inc.
9 * and on hummingboard.c which is :
10 * Copyright (C) 2013 SolidRun ltd.
11 * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>.
13 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/clock.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/arch/imx-regs.h>
19 #include <asm/arch/iomux.h>
20 #include <asm/arch/mx6-pins.h>
21 #include <linux/errno.h>
23 #include <asm/mach-imx/iomux-v3.h>
24 #include <asm/mach-imx/boot_mode.h>
25 #include <asm/mach-imx/mxc_i2c.h>
26 #include <asm/mach-imx/spi.h>
27 #include <asm/mach-imx/video.h>
31 #include <fsl_esdhc.h>
34 #include <asm/arch/mxc_hdmi.h>
35 #include <asm/arch/crm_regs.h>
37 #include <ipu_pixfmt.h>
40 DECLARE_GLOBAL_DATA_PTR;
42 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
43 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
44 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
46 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
47 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
48 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
50 #define USDHC_PAD_CLK_CTRL (PAD_CTL_SPEED_LOW | \
51 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \
54 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
55 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
57 #define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
58 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
60 #define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
61 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
63 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
64 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
65 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
67 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
68 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
70 static int board_type = -1;
71 #define BOARD_IS_MARSBOARD 0
72 #define BOARD_IS_RIOTBOARD 1
76 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
81 static iomux_v3_cfg_t const uart2_pads[] = {
82 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
83 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
86 static void setup_iomux_uart(void)
88 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
91 iomux_v3_cfg_t const enet_pads[] = {
92 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
93 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
94 /* GPIO16 -> AR8035 25MHz */
95 MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
96 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL),
97 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
98 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
99 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
100 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
101 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
102 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
103 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
104 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
105 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
106 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
107 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
108 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
109 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
110 /* AR8035 PHY Reset */
111 MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
112 /* AR8035 PHY Interrupt */
113 MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(ENET_PAD_CTRL),
116 static void setup_iomux_enet(void)
118 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
120 /* Reset AR8035 PHY */
121 gpio_direction_output(IMX_GPIO_NR(3, 31) , 0);
123 gpio_set_value(IMX_GPIO_NR(3, 31), 1);
126 int mx6_rgmii_rework(struct phy_device *phydev)
128 /* from linux/arch/arm/mach-imx/mach-imx6q.c :
129 * Ar803x phy SmartEEE feature cause link status generates glitch,
130 * which cause ethernet link down/up issue, so disable SmartEEE
132 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
133 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
134 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
139 int board_phy_config(struct phy_device *phydev)
141 mx6_rgmii_rework(phydev);
143 if (phydev->drv->config)
144 phydev->drv->config(phydev);
149 iomux_v3_cfg_t const usdhc2_pads[] = {
150 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
151 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
152 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
153 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
154 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
155 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
156 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
157 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
160 iomux_v3_cfg_t const usdhc3_pads[] = {
161 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
162 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
163 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
164 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
165 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
166 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
169 iomux_v3_cfg_t const riotboard_usdhc3_pads[] = {
170 MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
171 MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
174 iomux_v3_cfg_t const usdhc4_pads[] = {
175 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
176 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
177 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
178 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
179 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
180 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
182 MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
185 #ifdef CONFIG_FSL_ESDHC
186 struct fsl_esdhc_cfg usdhc_cfg[3] = {
192 #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
193 #define USDHC3_CD_GPIO IMX_GPIO_NR(7, 0)
195 int board_mmc_getcd(struct mmc *mmc)
197 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
200 switch (cfg->esdhc_base) {
201 case USDHC2_BASE_ADDR:
202 ret = !gpio_get_value(USDHC2_CD_GPIO);
204 case USDHC3_BASE_ADDR:
205 if (board_type == BOARD_IS_RIOTBOARD)
206 ret = !gpio_get_value(USDHC3_CD_GPIO);
207 else if (board_type == BOARD_IS_MARSBOARD)
208 ret = 1; /* eMMC/uSDHC3 is always present */
210 case USDHC4_BASE_ADDR:
211 ret = 1; /* eMMC/uSDHC4 is always present */
218 int board_mmc_init(bd_t *bis)
224 * According to the board_mmc_init() the following map is done:
225 * (U-Boot device node) (Physical Port)
227 * mmc0 SDCard slot (bottom)
228 * mmc1 uSDCard slot (top)
231 * mmc0 uSDCard slot (bottom)
234 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
237 imx_iomux_v3_setup_multiple_pads(
238 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
239 gpio_direction_input(USDHC2_CD_GPIO);
240 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
241 usdhc_cfg[0].max_bus_width = 4;
244 imx_iomux_v3_setup_multiple_pads(
245 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
246 if (board_type == BOARD_IS_RIOTBOARD) {
247 imx_iomux_v3_setup_multiple_pads(
248 riotboard_usdhc3_pads,
249 ARRAY_SIZE(riotboard_usdhc3_pads));
250 gpio_direction_input(USDHC3_CD_GPIO);
252 gpio_direction_output(IMX_GPIO_NR(7, 8) , 0);
254 gpio_set_value(IMX_GPIO_NR(7, 8), 1);
256 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
257 usdhc_cfg[1].max_bus_width = 4;
260 imx_iomux_v3_setup_multiple_pads(
261 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
262 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
263 usdhc_cfg[2].max_bus_width = 4;
264 gpio_direction_output(IMX_GPIO_NR(6, 8) , 0);
266 gpio_set_value(IMX_GPIO_NR(6, 8), 1);
269 printf("Warning: you configured more USDHC controllers"
270 "(%d) then supported by the board (%d)\n",
271 i + 1, CONFIG_SYS_FSL_USDHC_NUM);
275 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
284 #ifdef CONFIG_MXC_SPI
285 iomux_v3_cfg_t const ecspi1_pads[] = {
286 MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
287 MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
288 MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
289 MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
292 int board_spi_cs_gpio(unsigned bus, unsigned cs)
294 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
297 static void setup_spi(void)
299 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
303 struct i2c_pads_info i2c_pad_info1 = {
305 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL
306 | MUX_PAD_CTRL(I2C_PAD_CTRL),
307 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27
308 | MUX_PAD_CTRL(I2C_PAD_CTRL),
309 .gp = IMX_GPIO_NR(5, 27)
312 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA
313 | MUX_PAD_CTRL(I2C_PAD_CTRL),
314 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26
315 | MUX_PAD_CTRL(I2C_PAD_CTRL),
316 .gp = IMX_GPIO_NR(5, 26)
320 struct i2c_pads_info i2c_pad_info2 = {
322 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL
323 | MUX_PAD_CTRL(I2C_PAD_CTRL),
324 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12
325 | MUX_PAD_CTRL(I2C_PAD_CTRL),
326 .gp = IMX_GPIO_NR(4, 12)
329 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA
330 | MUX_PAD_CTRL(I2C_PAD_CTRL),
331 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13
332 | MUX_PAD_CTRL(I2C_PAD_CTRL),
333 .gp = IMX_GPIO_NR(4, 13)
337 struct i2c_pads_info i2c_pad_info3 = {
339 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL
340 | MUX_PAD_CTRL(I2C_PAD_CTRL),
341 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05
342 | MUX_PAD_CTRL(I2C_PAD_CTRL),
343 .gp = IMX_GPIO_NR(1, 5)
346 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA
347 | MUX_PAD_CTRL(I2C_PAD_CTRL),
348 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06
349 | MUX_PAD_CTRL(I2C_PAD_CTRL),
350 .gp = IMX_GPIO_NR(1, 6)
354 iomux_v3_cfg_t const tft_pads_riot[] = {
356 MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
358 MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
360 MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
362 MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
365 iomux_v3_cfg_t const tft_pads_mars[] = {
367 MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
369 MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
371 MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
372 /* BL LEVEL (PWM4) */
373 MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
376 #if defined(CONFIG_VIDEO_IPUV3)
378 static void enable_lvds(struct display_info_t const *dev)
380 struct iomuxc *iomux = (struct iomuxc *)
382 setbits_le32(&iomux->gpr[2],
383 IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT);
384 /* set backlight level to ON */
385 if (board_type == BOARD_IS_RIOTBOARD)
386 gpio_direction_output(IMX_GPIO_NR(1, 18) , 1);
387 else if (board_type == BOARD_IS_MARSBOARD)
388 gpio_direction_output(IMX_GPIO_NR(2, 10) , 1);
391 static void disable_lvds(struct display_info_t const *dev)
393 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
395 /* set backlight level to OFF */
396 if (board_type == BOARD_IS_RIOTBOARD)
397 gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
398 else if (board_type == BOARD_IS_MARSBOARD)
399 gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
401 clrbits_le32(&iomux->gpr[2],
402 IOMUXC_GPR2_LVDS_CH0_MODE_MASK);
405 static void do_enable_hdmi(struct display_info_t const *dev)
408 imx_enable_hdmi_phy();
411 static int detect_i2c(struct display_info_t const *dev)
413 return (0 == i2c_set_bus_num(dev->bus)) &&
414 (0 == i2c_probe(dev->addr));
417 struct display_info_t const displays[] = {{
420 .pixfmt = IPU_PIX_FMT_RGB24,
421 .detect = detect_hdmi,
422 .enable = do_enable_hdmi,
436 .vmode = FB_VMODE_NONINTERLACED
440 .pixfmt = IPU_PIX_FMT_LVDS666,
441 .detect = detect_i2c,
442 .enable = enable_lvds,
444 .name = "LCD8000-97C",
456 .vmode = FB_VMODE_NONINTERLACED
458 size_t display_count = ARRAY_SIZE(displays);
460 static void setup_display(void)
462 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
463 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
469 /* Turn on LDB0, IPU,IPU DI0 clocks */
470 setbits_le32(&mxc_ccm->CCGR3,
471 MXC_CCM_CCGR3_LDB_DI0_MASK);
473 /* set LDB0 clk select to 011/011 */
474 clrsetbits_le32(&mxc_ccm->cs2cdr,
475 MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK,
476 (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
478 setbits_le32(&mxc_ccm->cscmr2,
479 MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
481 setbits_le32(&mxc_ccm->chsccdr,
482 (CHSCCDR_CLK_SEL_LDB_DI0
483 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
485 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
486 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
487 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
488 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
489 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
490 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
491 | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
492 | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
493 writel(reg, &iomux->gpr[2]);
495 clrsetbits_le32(&iomux->gpr[3],
496 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
497 IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
498 IOMUXC_GPR3_MUX_SRC_IPU1_DI0
499 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
501 #endif /* CONFIG_VIDEO_IPUV3 */
504 * Do not overwrite the console
505 * Use always serial for U-Boot console
507 int overwrite_console(void)
512 int board_eth_init(bd_t *bis)
516 return cpu_eth_init(bis);
519 int board_early_init_f(void)
521 u32 cputype = cpu_type(get_cpu_rev());
524 case MXC_CPU_MX6SOLO:
525 board_type = BOARD_IS_RIOTBOARD;
528 board_type = BOARD_IS_MARSBOARD;
534 if (board_type == BOARD_IS_RIOTBOARD)
535 imx_iomux_v3_setup_multiple_pads(
536 tft_pads_riot, ARRAY_SIZE(tft_pads_riot));
537 else if (board_type == BOARD_IS_MARSBOARD)
538 imx_iomux_v3_setup_multiple_pads(
539 tft_pads_mars, ARRAY_SIZE(tft_pads_mars));
540 #if defined(CONFIG_VIDEO_IPUV3)
542 gpio_direction_output(IMX_GPIO_NR(1, 29) , 1);
543 /* touch interrupt is an input */
544 gpio_direction_input(IMX_GPIO_NR(6, 14));
545 /* power ON backlight */
546 gpio_direction_output(IMX_GPIO_NR(6, 15) , 1);
547 /* set backlight level to off */
548 if (board_type == BOARD_IS_RIOTBOARD)
549 gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
550 else if (board_type == BOARD_IS_MARSBOARD)
551 gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
560 /* address of boot parameters */
561 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
562 /* i2c1 : PMIC, Audio codec on RiOT, Expansion connector on MarS */
563 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
564 /* i2c2 : HDMI EDID */
565 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
566 /* i2c3 : LVDS, Expansion connector */
567 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
568 #ifdef CONFIG_MXC_SPI
574 #ifdef CONFIG_CMD_BMODE
575 static const struct boot_mode riotboard_boot_modes[] = {
576 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
577 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
578 {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
581 static const struct boot_mode marsboard_boot_modes[] = {
582 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
583 {"emmc", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
588 int board_late_init(void)
590 #ifdef CONFIG_CMD_BMODE
591 if (board_type == BOARD_IS_RIOTBOARD)
592 add_board_boot_modes(riotboard_boot_modes);
593 else if (board_type == BOARD_IS_RIOTBOARD)
594 add_board_boot_modes(marsboard_boot_modes);
603 if (board_type == BOARD_IS_MARSBOARD)
605 else if (board_type == BOARD_IS_RIOTBOARD)
608 printf("unknown - cputype : %02x\n", cpu_type(get_cpu_rev()));