2 * Copyright (C) 2014 Eukréa Electromatique
3 * Author: Eric Bénard <eric@eukrea.com>
4 * Fabio Estevam <fabio.estevam@freescale.com>
5 * Jon Nettleton <jon.nettleton@gmail.com>
7 * based on sabresd.c which is :
8 * Copyright (C) 2012 Freescale Semiconductor, Inc.
9 * and on hummingboard.c which is :
10 * Copyright (C) 2013 SolidRun ltd.
11 * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>.
13 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/clock.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/arch/imx-regs.h>
19 #include <asm/arch/iomux.h>
20 #include <asm/arch/mx6-pins.h>
21 #include <asm/errno.h>
23 #include <asm/imx-common/iomux-v3.h>
24 #include <asm/imx-common/boot_mode.h>
25 #include <asm/imx-common/mxc_i2c.h>
26 #include <asm/imx-common/spi.h>
27 #include <asm/imx-common/video.h>
30 #include <fsl_esdhc.h>
33 #include <asm/arch/mxc_hdmi.h>
34 #include <asm/arch/crm_regs.h>
36 #include <ipu_pixfmt.h>
38 #include <asm/arch/sys_proto.h>
39 DECLARE_GLOBAL_DATA_PTR;
41 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
42 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
43 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
45 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
46 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
47 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
49 #define USDHC_PAD_CLK_CTRL (PAD_CTL_SPEED_LOW | \
50 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \
53 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
54 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
56 #define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
57 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
59 #define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
60 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
62 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
63 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
64 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
66 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
67 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
69 static int board_type = -1;
70 #define BOARD_IS_MARSBOARD 0
71 #define BOARD_IS_RIOTBOARD 1
75 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
80 static iomux_v3_cfg_t const uart2_pads[] = {
81 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
82 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
85 static void setup_iomux_uart(void)
87 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
90 iomux_v3_cfg_t const enet_pads[] = {
91 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
92 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
93 /* GPIO16 -> AR8035 25MHz */
94 MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
95 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL),
96 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
97 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
98 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
99 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
100 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
101 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
102 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
103 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
104 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
105 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
106 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
107 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
108 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
109 /* AR8035 PHY Reset */
110 MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
111 /* AR8035 PHY Interrupt */
112 MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(ENET_PAD_CTRL),
115 static void setup_iomux_enet(void)
117 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
119 /* Reset AR8035 PHY */
120 gpio_direction_output(IMX_GPIO_NR(3, 31) , 0);
122 gpio_set_value(IMX_GPIO_NR(3, 31), 1);
125 int mx6_rgmii_rework(struct phy_device *phydev)
127 /* from linux/arch/arm/mach-imx/mach-imx6q.c :
128 * Ar803x phy SmartEEE feature cause link status generates glitch,
129 * which cause ethernet link down/up issue, so disable SmartEEE
131 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
132 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
133 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
138 int board_phy_config(struct phy_device *phydev)
140 mx6_rgmii_rework(phydev);
142 if (phydev->drv->config)
143 phydev->drv->config(phydev);
148 iomux_v3_cfg_t const usdhc2_pads[] = {
149 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
150 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
151 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
152 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
153 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
154 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
155 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
156 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
159 iomux_v3_cfg_t const usdhc3_pads[] = {
160 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
161 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
162 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
163 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
164 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
165 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
168 iomux_v3_cfg_t const riotboard_usdhc3_pads[] = {
169 MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
170 MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
173 iomux_v3_cfg_t const usdhc4_pads[] = {
174 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
175 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
176 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
177 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
178 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
179 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
181 MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
184 #ifdef CONFIG_FSL_ESDHC
185 struct fsl_esdhc_cfg usdhc_cfg[3] = {
191 #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
192 #define USDHC3_CD_GPIO IMX_GPIO_NR(7, 0)
194 int board_mmc_getcd(struct mmc *mmc)
196 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
199 switch (cfg->esdhc_base) {
200 case USDHC2_BASE_ADDR:
201 ret = !gpio_get_value(USDHC2_CD_GPIO);
203 case USDHC3_BASE_ADDR:
204 if (board_type == BOARD_IS_RIOTBOARD)
205 ret = !gpio_get_value(USDHC3_CD_GPIO);
206 else if (board_type == BOARD_IS_MARSBOARD)
207 ret = 1; /* eMMC/uSDHC3 is always present */
209 case USDHC4_BASE_ADDR:
210 ret = 1; /* eMMC/uSDHC4 is always present */
217 int board_mmc_init(bd_t *bis)
223 * According to the board_mmc_init() the following map is done:
224 * (U-boot device node) (Physical Port)
226 * mmc0 SDCard slot (bottom)
227 * mmc1 uSDCard slot (top)
230 * mmc0 uSDCard slot (bottom)
233 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
236 imx_iomux_v3_setup_multiple_pads(
237 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
238 gpio_direction_input(USDHC2_CD_GPIO);
239 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
240 usdhc_cfg[0].max_bus_width = 4;
243 imx_iomux_v3_setup_multiple_pads(
244 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
245 if (board_type == BOARD_IS_RIOTBOARD) {
246 imx_iomux_v3_setup_multiple_pads(
247 riotboard_usdhc3_pads,
248 ARRAY_SIZE(riotboard_usdhc3_pads));
249 gpio_direction_input(USDHC3_CD_GPIO);
251 gpio_direction_output(IMX_GPIO_NR(7, 8) , 0);
253 gpio_set_value(IMX_GPIO_NR(7, 8), 1);
255 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
256 usdhc_cfg[1].max_bus_width = 4;
259 imx_iomux_v3_setup_multiple_pads(
260 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
261 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
262 usdhc_cfg[2].max_bus_width = 4;
263 gpio_direction_output(IMX_GPIO_NR(6, 8) , 0);
265 gpio_set_value(IMX_GPIO_NR(6, 8), 1);
268 printf("Warning: you configured more USDHC controllers"
269 "(%d) then supported by the board (%d)\n",
270 i + 1, CONFIG_SYS_FSL_USDHC_NUM);
274 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
281 #ifdef CONFIG_MXC_SPI
282 iomux_v3_cfg_t const ecspi1_pads[] = {
283 MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
284 MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
285 MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
286 MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
289 int board_spi_cs_gpio(unsigned bus, unsigned cs)
291 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
294 static void setup_spi(void)
296 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
300 struct i2c_pads_info i2c_pad_info1 = {
302 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL
303 | MUX_PAD_CTRL(I2C_PAD_CTRL),
304 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27
305 | MUX_PAD_CTRL(I2C_PAD_CTRL),
306 .gp = IMX_GPIO_NR(5, 27)
309 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA
310 | MUX_PAD_CTRL(I2C_PAD_CTRL),
311 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26
312 | MUX_PAD_CTRL(I2C_PAD_CTRL),
313 .gp = IMX_GPIO_NR(5, 26)
317 struct i2c_pads_info i2c_pad_info2 = {
319 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL
320 | MUX_PAD_CTRL(I2C_PAD_CTRL),
321 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12
322 | MUX_PAD_CTRL(I2C_PAD_CTRL),
323 .gp = IMX_GPIO_NR(4, 12)
326 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA
327 | MUX_PAD_CTRL(I2C_PAD_CTRL),
328 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13
329 | MUX_PAD_CTRL(I2C_PAD_CTRL),
330 .gp = IMX_GPIO_NR(4, 13)
334 struct i2c_pads_info i2c_pad_info3 = {
336 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL
337 | MUX_PAD_CTRL(I2C_PAD_CTRL),
338 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05
339 | MUX_PAD_CTRL(I2C_PAD_CTRL),
340 .gp = IMX_GPIO_NR(1, 5)
343 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA
344 | MUX_PAD_CTRL(I2C_PAD_CTRL),
345 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06
346 | MUX_PAD_CTRL(I2C_PAD_CTRL),
347 .gp = IMX_GPIO_NR(1, 6)
351 iomux_v3_cfg_t const tft_pads_riot[] = {
353 MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
355 MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
357 MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
359 MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
362 iomux_v3_cfg_t const tft_pads_mars[] = {
364 MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
366 MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
368 MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
369 /* BL LEVEL (PWM4) */
370 MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
373 #if defined(CONFIG_VIDEO_IPUV3)
375 static void enable_lvds(struct display_info_t const *dev)
377 struct iomuxc *iomux = (struct iomuxc *)
379 setbits_le32(&iomux->gpr[2],
380 IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT);
381 /* set backlight level to ON */
382 if (board_type == BOARD_IS_RIOTBOARD)
383 gpio_direction_output(IMX_GPIO_NR(1, 18) , 1);
384 else if (board_type == BOARD_IS_MARSBOARD)
385 gpio_direction_output(IMX_GPIO_NR(2, 10) , 1);
388 static void disable_lvds(struct display_info_t const *dev)
390 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
392 /* set backlight level to OFF */
393 if (board_type == BOARD_IS_RIOTBOARD)
394 gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
395 else if (board_type == BOARD_IS_MARSBOARD)
396 gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
398 clrbits_le32(&iomux->gpr[2],
399 IOMUXC_GPR2_LVDS_CH0_MODE_MASK);
402 static void do_enable_hdmi(struct display_info_t const *dev)
405 imx_enable_hdmi_phy();
408 static int detect_i2c(struct display_info_t const *dev)
410 return (0 == i2c_set_bus_num(dev->bus)) &&
411 (0 == i2c_probe(dev->addr));
414 struct display_info_t const displays[] = {{
417 .pixfmt = IPU_PIX_FMT_RGB24,
418 .detect = detect_hdmi,
419 .enable = do_enable_hdmi,
433 .vmode = FB_VMODE_NONINTERLACED
437 .pixfmt = IPU_PIX_FMT_LVDS666,
438 .detect = detect_i2c,
439 .enable = enable_lvds,
441 .name = "LCD8000-97C",
453 .vmode = FB_VMODE_NONINTERLACED
455 size_t display_count = ARRAY_SIZE(displays);
457 static void setup_display(void)
459 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
460 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
466 /* Turn on LDB0, IPU,IPU DI0 clocks */
467 setbits_le32(&mxc_ccm->CCGR3,
468 MXC_CCM_CCGR3_LDB_DI0_MASK);
470 /* set LDB0 clk select to 011/011 */
471 clrsetbits_le32(&mxc_ccm->cs2cdr,
472 MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK,
473 (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
475 setbits_le32(&mxc_ccm->cscmr2,
476 MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
478 setbits_le32(&mxc_ccm->chsccdr,
479 (CHSCCDR_CLK_SEL_LDB_DI0
480 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
482 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
483 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
484 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
485 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
486 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
487 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
488 | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
489 | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
490 writel(reg, &iomux->gpr[2]);
492 clrsetbits_le32(&iomux->gpr[3],
493 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
494 IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
495 IOMUXC_GPR3_MUX_SRC_IPU1_DI0
496 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
498 #endif /* CONFIG_VIDEO_IPUV3 */
501 * Do not overwrite the console
502 * Use always serial for U-Boot console
504 int overwrite_console(void)
509 int board_eth_init(bd_t *bis)
513 return cpu_eth_init(bis);
516 int board_early_init_f(void)
518 u32 cputype = cpu_type(get_cpu_rev());
521 case MXC_CPU_MX6SOLO:
522 board_type = BOARD_IS_RIOTBOARD;
525 board_type = BOARD_IS_MARSBOARD;
531 if (board_type == BOARD_IS_RIOTBOARD)
532 imx_iomux_v3_setup_multiple_pads(
533 tft_pads_riot, ARRAY_SIZE(tft_pads_riot));
534 else if (board_type == BOARD_IS_MARSBOARD)
535 imx_iomux_v3_setup_multiple_pads(
536 tft_pads_mars, ARRAY_SIZE(tft_pads_mars));
537 #if defined(CONFIG_VIDEO_IPUV3)
539 gpio_direction_output(IMX_GPIO_NR(1, 29) , 1);
540 /* touch interrupt is an input */
541 gpio_direction_input(IMX_GPIO_NR(6, 14));
542 /* power ON backlight */
543 gpio_direction_output(IMX_GPIO_NR(6, 15) , 1);
544 /* set backlight level to off */
545 if (board_type == BOARD_IS_RIOTBOARD)
546 gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
547 else if (board_type == BOARD_IS_MARSBOARD)
548 gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
557 /* address of boot parameters */
558 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
559 /* i2c1 : PMIC, Audio codec on RiOT, Expansion connector on MarS */
560 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
561 /* i2c2 : HDMI EDID */
562 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
563 /* i2c3 : LVDS, Expansion connector */
564 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
565 #ifdef CONFIG_MXC_SPI
571 #ifdef CONFIG_CMD_BMODE
572 static const struct boot_mode riotboard_boot_modes[] = {
573 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
574 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
575 {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
578 static const struct boot_mode marsboard_boot_modes[] = {
579 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
580 {"emmc", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
585 int board_late_init(void)
587 #ifdef CONFIG_CMD_BMODE
588 if (board_type == BOARD_IS_RIOTBOARD)
589 add_board_boot_modes(riotboard_boot_modes);
590 else if (board_type == BOARD_IS_RIOTBOARD)
591 add_board_boot_modes(marsboard_boot_modes);
600 if (board_type == BOARD_IS_MARSBOARD)
602 else if (board_type == BOARD_IS_RIOTBOARD)
605 printf("unknown - cputype : %02x\n", cpu_type(get_cpu_rev()));