2 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
6 * SPDX-License-Identifier: GPL-2.0+
14 #include <linux/sizes.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/crm_regs.h>
18 #include <asm/arch/iomux.h>
19 #include <asm/arch/mx6-ddr.h>
20 #include <asm/arch/mx6-pins.h>
21 #include <asm/arch/sys_proto.h>
23 #include <asm/mach-imx/iomux-v3.h>
24 #include <asm/mach-imx/video.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
29 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
30 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
32 static iomux_v3_cfg_t const uart_pads[] = {
34 IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
35 IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
37 IOMUX_PADS(PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL)),
38 IOMUX_PADS(PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL)),
42 #ifdef CONFIG_SPL_LOAD_FIT
43 int board_fit_config_name_match(const char *name)
45 if (is_mx6dq() && !strcmp(name, "imx6q-icore"))
47 else if (is_mx6dq() && !strcmp(name, "imx6q-icore-rqs"))
49 else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore"))
51 else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-rqs"))
58 #ifdef CONFIG_ENV_IS_IN_MMC
59 void board_boot_order(u32 *spl_boot_list)
61 u32 bmode = imx6_src_get_boot_mode();
62 u8 boot_dev = BOOT_DEVICE_MMC1;
64 switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
67 /* SD/eSD - BOOT_DEVICE_MMC1 */
72 boot_dev = BOOT_DEVICE_MMC2;
75 /* Default - BOOT_DEVICE_MMC1 */
76 printf("Wrong board boot order\n");
80 spl_boot_list[0] = boot_dev;
84 #ifdef CONFIG_SPL_OS_BOOT
85 int spl_start_uboot(void)
87 /* break into full u-boot on 'c' */
88 if (serial_tstc() && serial_getc() == 'c')
101 #define IMX6DQ_DRIVE_STRENGTH 0x30
102 #define IMX6SDL_DRIVE_STRENGTH 0x28
104 /* configure MX6Q/DUAL mmdc DDR io registers */
105 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
106 .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
107 .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
108 .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
109 .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
110 .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
111 .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
112 .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
113 .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
114 .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
115 .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
116 .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
117 .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
118 .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
119 .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
120 .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
121 .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
122 .dram_cas = IMX6DQ_DRIVE_STRENGTH,
123 .dram_ras = IMX6DQ_DRIVE_STRENGTH,
124 .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
125 .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
126 .dram_reset = IMX6DQ_DRIVE_STRENGTH,
127 .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
128 .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
129 .dram_sdba2 = 0x00000000,
130 .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
131 .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
134 /* configure MX6Q/DUAL mmdc GRP io registers */
135 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
136 .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
137 .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
138 .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
139 .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
140 .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
141 .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
142 .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
143 .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
144 .grp_addds = IMX6DQ_DRIVE_STRENGTH,
145 .grp_ddrmode_ctl = 0x00020000,
146 .grp_ddrpke = 0x00000000,
147 .grp_ddrmode = 0x00020000,
148 .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
149 .grp_ddr_type = 0x000c0000,
152 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
153 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
154 .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
155 .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
156 .dram_cas = IMX6SDL_DRIVE_STRENGTH,
157 .dram_ras = IMX6SDL_DRIVE_STRENGTH,
158 .dram_reset = IMX6SDL_DRIVE_STRENGTH,
159 .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
160 .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
161 .dram_sdba2 = 0x00000000,
162 .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
163 .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
164 .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
165 .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
166 .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
167 .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
168 .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
169 .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
170 .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
171 .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
172 .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
173 .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
174 .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
175 .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
176 .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
177 .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
178 .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
179 .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
182 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
183 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
184 .grp_ddr_type = 0x000c0000,
185 .grp_ddrmode_ctl = 0x00020000,
186 .grp_ddrpke = 0x00000000,
187 .grp_addds = IMX6SDL_DRIVE_STRENGTH,
188 .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
189 .grp_ddrmode = 0x00020000,
190 .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
191 .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
192 .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
193 .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
194 .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
195 .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
196 .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
197 .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
201 static struct mx6_ddr3_cfg mt41j256 = {
215 static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
216 .p0_mpwldectrl0 = 0x000E0009,
217 .p0_mpwldectrl1 = 0x0018000E,
218 .p1_mpwldectrl0 = 0x00000007,
219 .p1_mpwldectrl1 = 0x00000000,
220 .p0_mpdgctrl0 = 0x43280334,
221 .p0_mpdgctrl1 = 0x031C0314,
222 .p1_mpdgctrl0 = 0x4318031C,
223 .p1_mpdgctrl1 = 0x030C0258,
224 .p0_mprddlctl = 0x3E343A40,
225 .p1_mprddlctl = 0x383C3844,
226 .p0_mpwrdlctl = 0x40404440,
227 .p1_mpwrdlctl = 0x4C3E4446,
231 static struct mx6_ddr_sysinfo mem_q = {
232 .ddr_type = DDR_TYPE_DDR3,
235 /* config for full 4GB range so that get_mem_size() works */
248 static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
249 .p0_mpwldectrl0 = 0x001F0024,
250 .p0_mpwldectrl1 = 0x00110018,
251 .p1_mpwldectrl0 = 0x001F0024,
252 .p1_mpwldectrl1 = 0x00110018,
253 .p0_mpdgctrl0 = 0x4230022C,
254 .p0_mpdgctrl1 = 0x02180220,
255 .p1_mpdgctrl0 = 0x42440248,
256 .p1_mpdgctrl1 = 0x02300238,
257 .p0_mprddlctl = 0x44444A48,
258 .p1_mprddlctl = 0x46484A42,
259 .p0_mpwrdlctl = 0x38383234,
260 .p1_mpwrdlctl = 0x3C34362E,
264 static struct mx6_ddr_sysinfo mem_dl = {
267 /* config for full 4GB range so that get_mem_size() works */
280 /* DDR 32bit 512MB */
281 static struct mx6_ddr_sysinfo mem_s = {
284 /* config for full 4GB range so that get_mem_size() works */
296 #endif /* CONFIG_MX6QDL */
299 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
300 .grp_addds = 0x00000030,
301 .grp_ddrmode_ctl = 0x00020000,
302 .grp_b0ds = 0x00000030,
303 .grp_ctlds = 0x00000030,
304 .grp_b1ds = 0x00000030,
305 .grp_ddrpke = 0x00000000,
306 .grp_ddrmode = 0x00020000,
307 .grp_ddr_type = 0x000c0000,
310 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
311 .dram_dqm0 = 0x00000030,
312 .dram_dqm1 = 0x00000030,
313 .dram_ras = 0x00000030,
314 .dram_cas = 0x00000030,
315 .dram_odt0 = 0x00000030,
316 .dram_odt1 = 0x00000030,
317 .dram_sdba2 = 0x00000000,
318 .dram_sdclk_0 = 0x00000008,
319 .dram_sdqs0 = 0x00000038,
320 .dram_sdqs1 = 0x00000030,
321 .dram_reset = 0x00000030,
324 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
325 .p0_mpwldectrl0 = 0x00070007,
326 .p0_mpdgctrl0 = 0x41490145,
327 .p0_mprddlctl = 0x40404546,
328 .p0_mpwrdlctl = 0x4040524D,
331 struct mx6_ddr_sysinfo ddr_sysinfo = {
337 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
338 .walat = 1, /* Write additional latency */
339 .ralat = 5, /* Read additional latency */
340 .mif3_mode = 3, /* Command prediction working mode */
341 .bi_on = 1, /* Bank interleaving enabled */
342 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
343 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
344 .ddr_type = DDR_TYPE_DDR3,
347 static struct mx6_ddr3_cfg mem_ddr = {
352 #ifdef TARGET_MX6UL_ISIOT
363 #endif /* CONFIG_MX6UL */
365 static void ccgr_init(void)
367 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
370 writel(0x00003F3F, &ccm->CCGR0);
371 writel(0x0030FC00, &ccm->CCGR1);
372 writel(0x000FC000, &ccm->CCGR2);
373 writel(0x3F300000, &ccm->CCGR3);
374 writel(0xFF00F300, &ccm->CCGR4);
375 writel(0x0F0000C3, &ccm->CCGR5);
376 writel(0x000003CC, &ccm->CCGR6);
378 writel(0x00c03f3f, &ccm->CCGR0);
379 writel(0xfcffff00, &ccm->CCGR1);
380 writel(0x0cffffcc, &ccm->CCGR2);
381 writel(0x3f3c3030, &ccm->CCGR3);
382 writel(0xff00fffc, &ccm->CCGR4);
383 writel(0x033f30ff, &ccm->CCGR5);
384 writel(0x00c00fff, &ccm->CCGR6);
388 static void spl_dram_init(void)
392 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
393 mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
394 } else if (is_mx6dl()) {
395 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
396 mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
397 } else if (is_mx6dq()) {
398 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
399 mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
402 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
403 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
409 void board_init_f(ulong dummy)
413 /* setup AIPS and disable watchdog */
419 SETUP_IOMUX_PADS(uart_pads);
424 /* UART clocks enabled and gd valid - init serial console */
425 preloader_console_init();
427 /* DDR initialization */