2 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
6 * SPDX-License-Identifier: GPL-2.0+
14 #include <linux/sizes.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/crm_regs.h>
18 #include <asm/arch/iomux.h>
19 #include <asm/arch/mx6-pins.h>
20 #include <asm/arch/sys_proto.h>
21 #include <asm/imx-common/iomux-v3.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 #ifdef CONFIG_NAND_MXS
27 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
28 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
30 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
32 static iomux_v3_cfg_t const nand_pads[] = {
33 IOMUX_PADS(PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
34 IOMUX_PADS(PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
35 IOMUX_PADS(PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
36 IOMUX_PADS(PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
37 IOMUX_PADS(PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
38 IOMUX_PADS(PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
39 IOMUX_PADS(PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
40 IOMUX_PADS(PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
41 IOMUX_PADS(PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
42 IOMUX_PADS(PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
43 IOMUX_PADS(PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
44 IOMUX_PADS(PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
45 IOMUX_PADS(PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
46 IOMUX_PADS(PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
47 IOMUX_PADS(PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
50 static void setup_gpmi_nand(void)
52 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
54 /* config gpmi nand iomux */
55 SETUP_IOMUX_PADS(nand_pads);
57 clrbits_le32(&mxc_ccm->CCGR4,
58 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
59 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
60 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
61 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
62 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
65 * config gpmi and bch clock to 100 MHz
66 * bch/gpmi select PLL2 PFD2 400M
69 clrbits_le32(&mxc_ccm->cscmr1,
70 MXC_CCM_CSCMR1_BCH_CLK_SEL |
71 MXC_CCM_CSCMR1_GPMI_CLK_SEL);
72 clrsetbits_le32(&mxc_ccm->cscdr1,
73 MXC_CCM_CSCDR1_BCH_PODF_MASK |
74 MXC_CCM_CSCDR1_GPMI_PODF_MASK,
75 (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
76 (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
78 /* enable gpmi and bch clock gating */
79 setbits_le32(&mxc_ccm->CCGR4,
80 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
81 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
82 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
83 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
84 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
86 /* enable apbh clock gating */
87 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
89 #endif /* CONFIG_NAND_MXS */
91 #ifdef CONFIG_ENV_IS_IN_MMC
92 static void mmc_late_init(void)
96 u32 dev_no = mmc_get_env_dev();
98 setenv_ulong("mmcdev", dev_no);
101 sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no);
102 setenv("mmcroot", mmcblk);
104 sprintf(cmd, "mmc dev %d", dev_no);
109 int board_late_init(void)
111 switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
115 #ifdef CONFIG_ENV_IS_IN_MMC
118 setenv("modeboot", "mmcboot");
120 case IMX6_BMODE_NAND:
121 setenv("modeboot", "nandboot");
124 setenv("modeboot", "");
129 setenv("fdt_file", "imx6ul-geam-kit.dtb");
136 /* Address of boot parameters */
137 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
139 #ifdef CONFIG_NAND_MXS
148 gd->ram_size = imx_ddr_size();
153 #ifdef CONFIG_SPL_BUILD
154 /* MMC board initialization is needed till adding DM support in SPL */
155 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
157 #include <fsl_esdhc.h>
159 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
160 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
161 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
163 static iomux_v3_cfg_t const usdhc1_pads[] = {
164 IOMUX_PADS(PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
165 IOMUX_PADS(PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
166 IOMUX_PADS(PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
167 IOMUX_PADS(PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
168 IOMUX_PADS(PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
169 IOMUX_PADS(PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
172 IOMUX_PADS(PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
174 IOMUX_PADS(PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
176 IOMUX_PADS(PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
179 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
181 struct fsl_esdhc_cfg usdhc_cfg[1] = {
182 {USDHC1_BASE_ADDR, 0, 4},
185 int board_mmc_getcd(struct mmc *mmc)
187 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
190 switch (cfg->esdhc_base) {
191 case USDHC1_BASE_ADDR:
192 ret = !gpio_get_value(USDHC1_CD_GPIO);
199 int board_mmc_init(bd_t *bis)
204 * According to the board_mmc_init() the following map is done:
205 * (U-boot device node) (Physical Port)
208 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
211 SETUP_IOMUX_PADS(usdhc1_pads);
212 gpio_direction_input(USDHC1_CD_GPIO);
213 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
216 printf("Warning - USDHC%d controller not supporting\n",
221 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
223 printf("Warning: failed to initialize mmc dev %d\n", i);
230 #endif /* CONFIG_FSL_ESDHC */
231 #endif /* CONFIG_SPL_BUILD */