git.sur5r.net Git - u-boot/blob - board/engicam/geam6ul/geam6ul.c

   1 /*
   2  * Copyright (C) 2016 Amarula Solutions B.V.
   3  * Copyright (C) 2016 Engicam S.r.l.
   4  * Author: Jagan Teki <jagan@amarulasolutions.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10
  11 #include <asm/io.h>
  12 #include <asm/gpio.h>
  13 #include <linux/sizes.h>
  14
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/crm_regs.h>
  17 #include <asm/arch/iomux.h>
  18 #include <asm/arch/mx6-pins.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/imx-common/iomux-v3.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  25         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  26         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  27
  28 static iomux_v3_cfg_t const uart1_pads[] = {
  29         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  30         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  31 };
  32
  33 int board_early_init_f(void)
  34 {
  35         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  36
  37         return 0;
  38 }
  39
  40 #ifdef CONFIG_NAND_MXS
  41
  42 #define GPMI_PAD_CTRL0          (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
  43 #define GPMI_PAD_CTRL1          (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
  44                                 PAD_CTL_SRE_FAST)
  45 #define GPMI_PAD_CTRL2          (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
  46
  47 static iomux_v3_cfg_t const nand_pads[] = {
  48         MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  49         MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  50         MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  51         MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  52         MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  53         MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  54         MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  55         MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  56         MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  57         MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  58         MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  59         MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  60         MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  61         MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  62         MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  63 };
  64
  65 static void setup_gpmi_nand(void)
  66 {
  67         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  68
  69         /* config gpmi nand iomux */
  70         imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
  71
  72         clrbits_le32(&mxc_ccm->CCGR4,
  73                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  74                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  75                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  76                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  77                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  78
  79         /*
  80          * config gpmi and bch clock to 100 MHz
  81          * bch/gpmi select PLL2 PFD2 400M
  82          * 100M = 400M / 4
  83          */
  84         clrbits_le32(&mxc_ccm->cscmr1,
  85                      MXC_CCM_CSCMR1_BCH_CLK_SEL |
  86                      MXC_CCM_CSCMR1_GPMI_CLK_SEL);
  87         clrsetbits_le32(&mxc_ccm->cscdr1,
  88                         MXC_CCM_CSCDR1_BCH_PODF_MASK |
  89                         MXC_CCM_CSCDR1_GPMI_PODF_MASK,
  90                         (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
  91                         (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
  92
  93         /* enable gpmi and bch clock gating */
  94         setbits_le32(&mxc_ccm->CCGR4,
  95                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  96                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  97                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  98                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  99                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
 100
 101         /* enable apbh clock gating */
 102         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 103 }
 104 #endif /* CONFIG_NAND_MXS */
 105
 106 int board_late_init(void)
 107 {
 108         switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
 109                         IMX6_BMODE_SHIFT) {
 110         case IMX6_BMODE_SD:
 111         case IMX6_BMODE_ESD:
 112                 setenv("modeboot", "mmcboot");
 113                 break;
 114         case IMX6_BMODE_NAND:
 115                 setenv("modeboot", "nandboot");
 116                 break;
 117         default:
 118                 setenv("modeboot", "");
 119                 break;
 120         }
 121
 122         return 0;
 123 }
 124
 125 int board_init(void)
 126 {
 127         /* Address of boot parameters */
 128         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 129
 130 #ifdef CONFIG_NAND_MXS
 131         setup_gpmi_nand();
 132 #endif
 133
 134         return 0;
 135 }
 136
 137 int dram_init(void)
 138 {
 139         gd->ram_size = imx_ddr_size();
 140
 141         return 0;
 142 }
 143
 144 #ifdef CONFIG_SPL_BUILD
 145 #include <libfdt.h>
 146 #include <spl.h>
 147
 148 #include <asm/arch/crm_regs.h>
 149 #include <asm/arch/mx6-ddr.h>
 150
 151 /* MMC board initialization is needed till adding DM support in SPL */
 152 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
 153 #include <mmc.h>
 154 #include <fsl_esdhc.h>
 155
 156 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
 157         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
 158         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 159
 160 static iomux_v3_cfg_t const usdhc1_pads[] = {
 161         MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 162         MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 163         MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 164         MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 165         MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 166         MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 167
 168         /* VSELECT */
 169         MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 170         /* CD */
 171         MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
 172         /* RST_B */
 173         MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
 174 };
 175
 176 #define USDHC1_CD_GPIO  IMX_GPIO_NR(1, 1)
 177
 178 struct fsl_esdhc_cfg usdhc_cfg[1] = {
 179         {USDHC1_BASE_ADDR, 0, 4},
 180 };
 181
 182 int board_mmc_getcd(struct mmc *mmc)
 183 {
 184         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 185         int ret = 0;
 186
 187         switch (cfg->esdhc_base) {
 188         case USDHC1_BASE_ADDR:
 189                 ret = !gpio_get_value(USDHC1_CD_GPIO);
 190                 break;
 191         }
 192
 193         return ret;
 194 }
 195
 196 int board_mmc_init(bd_t *bis)
 197 {
 198         int i, ret;
 199
 200         /*
 201         * According to the board_mmc_init() the following map is done:
 202         * (U-boot device node)    (Physical Port)
 203         * mmc0                          USDHC1
 204         */
 205         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 206                 switch (i) {
 207                 case 0:
 208                         imx_iomux_v3_setup_multiple_pads(
 209                                 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 210                         gpio_direction_input(USDHC1_CD_GPIO);
 211                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 212                         break;
 213                 default:
 214                         printf("Warning - USDHC%d controller not supporting\n",
 215                                i + 1);
 216                         return 0;
 217                 }
 218
 219                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 220                 if (ret) {
 221                         printf("Warning: failed to initialize mmc dev %d\n", i);
 222                         return ret;
 223                 }
 224         }
 225
 226         return 0;
 227 }
 228 #endif /* CONFIG_FSL_ESDHC */
 229
 230 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
 231         .grp_addds = 0x00000030,
 232         .grp_ddrmode_ctl = 0x00020000,
 233         .grp_b0ds = 0x00000030,
 234         .grp_ctlds = 0x00000030,
 235         .grp_b1ds = 0x00000030,
 236         .grp_ddrpke = 0x00000000,
 237         .grp_ddrmode = 0x00020000,
 238         .grp_ddr_type = 0x000c0000,
 239 };
 240
 241 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
 242         .dram_dqm0 = 0x00000030,
 243         .dram_dqm1 = 0x00000030,
 244         .dram_ras = 0x00000030,
 245         .dram_cas = 0x00000030,
 246         .dram_odt0 = 0x00000030,
 247         .dram_odt1 = 0x00000030,
 248         .dram_sdba2 = 0x00000000,
 249         .dram_sdclk_0 = 0x00000008,
 250         .dram_sdqs0 = 0x00000038,
 251         .dram_sdqs1 = 0x00000030,
 252         .dram_reset = 0x00000030,
 253 };
 254
 255 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
 256         .p0_mpwldectrl0 = 0x00070007,
 257         .p0_mpdgctrl0 = 0x41490145,
 258         .p0_mprddlctl = 0x40404546,
 259         .p0_mpwrdlctl = 0x4040524D,
 260 };
 261
 262 struct mx6_ddr_sysinfo ddr_sysinfo = {
 263         .dsize = 0,
 264         .cs_density = 20,
 265         .ncs = 1,
 266         .cs1_mirror = 0,
 267         .rtt_wr = 2,
 268         .rtt_nom = 1,           /* RTT_Nom = RZQ/2 */
 269         .walat = 1,             /* Write additional latency */
 270         .ralat = 5,             /* Read additional latency */
 271         .mif3_mode = 3,         /* Command prediction working mode */
 272         .bi_on = 1,             /* Bank interleaving enabled */
 273         .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 274         .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 275         .ddr_type = DDR_TYPE_DDR3,
 276 };
 277
 278 static struct mx6_ddr3_cfg mem_ddr = {
 279         .mem_speed = 800,
 280         .density = 4,
 281         .width = 16,
 282         .banks = 8,
 283         .rowaddr = 13,
 284         .coladdr = 10,
 285         .pagesz = 2,
 286         .trcd = 1375,
 287         .trcmin = 4875,
 288         .trasmin = 3500,
 289 };
 290
 291 static void ccgr_init(void)
 292 {
 293         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 294
 295         writel(0xFFFFFFFF, &ccm->CCGR0);
 296         writel(0xFFFFFFFF, &ccm->CCGR1);
 297         writel(0xFFFFFFFF, &ccm->CCGR2);
 298         writel(0xFFFFFFFF, &ccm->CCGR3);
 299         writel(0xFFFFFFFF, &ccm->CCGR4);
 300         writel(0xFFFFFFFF, &ccm->CCGR5);
 301         writel(0xFFFFFFFF, &ccm->CCGR6);
 302         writel(0xFFFFFFFF, &ccm->CCGR7);
 303 }
 304
 305 static void spl_dram_init(void)
 306 {
 307         mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 308         mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
 309 }
 310
 311 void board_init_f(ulong dummy)
 312 {
 313         /* setup AIPS and disable watchdog */
 314         arch_cpu_init();
 315
 316         ccgr_init();
 317
 318         /* iomux and setup of i2c */
 319         board_early_init_f();
 320
 321         /* setup GP timer */
 322         timer_init();
 323
 324         /* UART clocks enabled and gd valid - init serial console */
 325         preloader_console_init();
 326
 327         /* DDR initialization */
 328         spl_dram_init();
 329
 330         /* Clear the BSS. */
 331         memset(__bss_start, 0, __bss_end - __bss_start);
 332
 333         /* load/boot image from boot device */
 334         board_init_r(NULL, 0);
 335 }
 336 #endif /* CONFIG_SPL_BUILD */