2 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
6 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/sizes.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/crm_regs.h>
17 #include <asm/arch/iomux.h>
18 #include <asm/arch/mx6-pins.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/imx-common/iomux-v3.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
25 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
26 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
28 static iomux_v3_cfg_t const uart1_pads[] = {
29 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
30 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
33 int board_early_init_f(void)
35 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
40 #ifdef CONFIG_NAND_MXS
42 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
43 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
45 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
47 static iomux_v3_cfg_t const nand_pads[] = {
48 MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
49 MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
50 MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
51 MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
52 MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
53 MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
54 MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
55 MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
56 MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
57 MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
58 MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
59 MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
60 MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
61 MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
62 MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
65 static void setup_gpmi_nand(void)
67 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
69 /* config gpmi nand iomux */
70 imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
72 clrbits_le32(&mxc_ccm->CCGR4,
73 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
74 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
75 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
76 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
77 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
80 * config gpmi and bch clock to 100 MHz
81 * bch/gpmi select PLL2 PFD2 400M
84 clrbits_le32(&mxc_ccm->cscmr1,
85 MXC_CCM_CSCMR1_BCH_CLK_SEL |
86 MXC_CCM_CSCMR1_GPMI_CLK_SEL);
87 clrsetbits_le32(&mxc_ccm->cscdr1,
88 MXC_CCM_CSCDR1_BCH_PODF_MASK |
89 MXC_CCM_CSCDR1_GPMI_PODF_MASK,
90 (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
91 (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
93 /* enable gpmi and bch clock gating */
94 setbits_le32(&mxc_ccm->CCGR4,
95 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
96 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
97 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
98 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
99 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
101 /* enable apbh clock gating */
102 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
104 #endif /* CONFIG_NAND_MXS */
106 int board_late_init(void)
108 switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
113 case IMX6_BMODE_EMMC:
114 setenv("modeboot", "mmcboot");
116 case IMX6_BMODE_NAND:
117 setenv("modeboot", "nandboot");
120 setenv("modeboot", "");
129 /* Address of boot parameters */
130 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
132 #ifdef CONFIG_NAND_MXS
140 gd->ram_size = imx_ddr_size();
145 #ifdef CONFIG_SPL_BUILD
149 #include <asm/arch/crm_regs.h>
150 #include <asm/arch/mx6-ddr.h>
152 /* MMC board initialization is needed till adding DM support in SPL */
153 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
155 #include <fsl_esdhc.h>
157 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
158 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
159 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
161 static iomux_v3_cfg_t const usdhc1_pads[] = {
162 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
163 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
164 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
165 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
166 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
167 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
170 MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
172 MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
174 MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
177 static iomux_v3_cfg_t const usdhc2_pads[] = {
178 MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
179 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
180 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
181 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
182 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
183 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
184 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
185 MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
186 MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
189 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
190 #define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5)
192 struct fsl_esdhc_cfg usdhc_cfg[2] = {
193 {USDHC1_BASE_ADDR, 0, 4},
194 {USDHC2_BASE_ADDR, 0, 8},
197 int board_mmc_getcd(struct mmc *mmc)
199 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
202 switch (cfg->esdhc_base) {
203 case USDHC1_BASE_ADDR:
204 ret = !gpio_get_value(USDHC1_CD_GPIO);
206 case USDHC2_BASE_ADDR:
207 ret = !gpio_get_value(USDHC2_CD_GPIO);
214 int board_mmc_init(bd_t *bis)
219 * According to the board_mmc_init() the following map is done:
220 * (U-boot device node) (Physical Port)
224 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
227 imx_iomux_v3_setup_multiple_pads(
228 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
229 gpio_direction_input(USDHC1_CD_GPIO);
230 usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
233 imx_iomux_v3_setup_multiple_pads(
234 usdhc1_pads, ARRAY_SIZE(usdhc2_pads));
235 gpio_direction_input(USDHC2_CD_GPIO);
236 usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
239 printf("Warning - USDHC%d controller not supporting\n",
244 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
246 printf("Warning: failed to initialize mmc dev %d\n", i);
254 #ifdef CONFIG_ENV_IS_IN_MMC
255 void board_boot_order(u32 *spl_boot_list)
257 u32 bmode = imx6_src_get_boot_mode();
258 u8 boot_dev = BOOT_DEVICE_MMC1;
260 switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
263 /* SD/eSD - BOOT_DEVICE_MMC1 */
266 case IMX6_BMODE_EMMC:
268 boot_dev = BOOT_DEVICE_MMC2;
271 /* Default - BOOT_DEVICE_MMC1 */
272 printf("Wrong board boot order\n");
276 spl_boot_list[0] = boot_dev;
279 #endif /* CONFIG_FSL_ESDHC */
281 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
282 .grp_addds = 0x00000030,
283 .grp_ddrmode_ctl = 0x00020000,
284 .grp_b0ds = 0x00000030,
285 .grp_ctlds = 0x00000030,
286 .grp_b1ds = 0x00000030,
287 .grp_ddrpke = 0x00000000,
288 .grp_ddrmode = 0x00020000,
289 .grp_ddr_type = 0x000c0000,
292 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
293 .dram_dqm0 = 0x00000030,
294 .dram_dqm1 = 0x00000030,
295 .dram_ras = 0x00000030,
296 .dram_cas = 0x00000030,
297 .dram_odt0 = 0x00000030,
298 .dram_odt1 = 0x00000030,
299 .dram_sdba2 = 0x00000000,
300 .dram_sdclk_0 = 0x00000008,
301 .dram_sdqs0 = 0x00000038,
302 .dram_sdqs1 = 0x00000030,
303 .dram_reset = 0x00000030,
306 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
307 .p0_mpwldectrl0 = 0x00070007,
308 .p0_mpdgctrl0 = 0x41490145,
309 .p0_mprddlctl = 0x40404546,
310 .p0_mpwrdlctl = 0x4040524D,
313 struct mx6_ddr_sysinfo ddr_sysinfo = {
319 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
320 .walat = 1, /* Write additional latency */
321 .ralat = 5, /* Read additional latency */
322 .mif3_mode = 3, /* Command prediction working mode */
323 .bi_on = 1, /* Bank interleaving enabled */
324 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
325 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
326 .ddr_type = DDR_TYPE_DDR3,
329 static struct mx6_ddr3_cfg mem_ddr = {
342 static void ccgr_init(void)
344 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
346 writel(0x00c03f3f, &ccm->CCGR0);
347 writel(0xfcffff00, &ccm->CCGR1);
348 writel(0x0cffffcc, &ccm->CCGR2);
349 writel(0x3f3c3030, &ccm->CCGR3);
350 writel(0xff00fffc, &ccm->CCGR4);
351 writel(0x033f30ff, &ccm->CCGR5);
352 writel(0x00c00fff, &ccm->CCGR6);
355 static void spl_dram_init(void)
357 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
358 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
361 void board_init_f(ulong dummy)
363 /* setup AIPS and disable watchdog */
368 /* iomux and setup of i2c */
369 board_early_init_f();
374 /* UART clocks enabled and gd valid - init serial console */
375 preloader_console_init();
377 /* DDR initialization */
381 memset(__bss_start, 0, __bss_end - __bss_start);
383 /* load/boot image from boot device */
384 board_init_r(NULL, 0);
386 #endif /* CONFIG_SPL_BUILD */