2 * (C) Copyright 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
8 * SPDX-License-Identifier: GPL-2.0+
16 * I/O Port configuration table
18 * if conf is 1, then that port pin will be configured at boot time
19 * according to the five values podr/pdir/ppar/psor/pdat for that entry
22 const iop_conf_t iop_conf_tab[4][32] = {
24 /* Port A configuration */
25 { /* conf ppar psor pdir podr pdat */
26 /* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* */
27 /* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* */
28 /* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* */
29 /* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* */
30 /* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* */
31 /* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* */
32 /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* */
33 /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* */
34 /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* */
35 /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* */
36 /* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* */
37 /* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* */
38 /* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* */
39 /* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* */
40 /* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* */
41 /* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* */
42 /* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* */
43 /* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* */
44 /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* */
45 /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* */
46 /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* */
47 /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* */
48 /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* */
49 /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* */
50 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
51 /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
52 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
53 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
54 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
55 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
56 /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
57 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
60 /* Port B configuration */
61 { /* conf ppar psor pdir podr pdat */
62 /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* */
63 /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* */
64 /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* */
65 /* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* */
66 /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* */
67 /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* */
68 /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* */
69 /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* */
70 /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* */
71 /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* */
72 /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* */
73 /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* */
74 /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* */
75 /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* */
76 /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */
77 /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */
78 /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */
79 /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */
80 /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */
81 /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */
82 /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */
83 /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */
84 /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */
85 /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */
86 /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
87 /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */
88 /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */
89 /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */
90 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
91 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
92 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
93 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
97 { /* conf ppar psor pdir podr pdat */
98 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
99 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
100 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* */
101 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
102 /* PC27 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */
103 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
104 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
105 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
106 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* */
107 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* */
108 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* */
109 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* */
110 /* PC19 */ { 0, 1, 0, 0, 0, 0 }, /* */
111 /* PC18 */ { 0, 1, 0, 0, 0, 0 }, /* */
112 /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CLK15 */
113 /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CLK16 */
114 /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
115 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* */
116 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
117 /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */
118 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */
119 /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* */
120 /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* */
121 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
122 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
123 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
124 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
125 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
126 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
127 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* */
128 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* */
129 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* */
133 { /* conf ppar psor pdir podr pdat */
134 /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* */
135 /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* */
136 /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* */
137 /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
138 /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */
139 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
140 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
141 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
142 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
143 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
144 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
145 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
146 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
147 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
148 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* */
149 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* */
150 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
151 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
152 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
153 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
154 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
155 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
156 /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
157 /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
158 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
159 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
160 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
161 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
162 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
163 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
164 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
165 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
169 /* ------------------------------------------------------------------------- */
172 * Setup CS4 to enable the Board Control/Status registers.
173 * Otherwise the smcs won't work.
175 int board_early_init_f (void)
177 volatile t_ep_regs *regs = (t_ep_regs *) CONFIG_SYS_REGS_BASE;
178 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
179 volatile memctl8260_t *memctl = &immap->im_memctl;
181 memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
182 memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
183 regs->bcsr1 = 0x62; /* to enable terminal on SMC1 */
184 regs->bcsr2 = 0x30; /* enable NVRAM and writing FLASH */
188 void reset_phy (void)
190 volatile t_ep_regs *regs = (t_ep_regs *) CONFIG_SYS_REGS_BASE;
196 * Check Board Identity:
197 * I don' know, how the next board revisions will be coded.
198 * Thats why its a static interpretation ...
201 int checkboard (void)
203 volatile t_ep_regs *regs = (t_ep_regs *) CONFIG_SYS_REGS_BASE;
204 uint major = 0, minor = 0;
206 switch (regs->bcsr0) {
221 printf ("Board: Embedded Planet EP8260, Revision %d.%d\n",
227 /* ------------------------------------------------------------------------- */
230 phys_size_t initdram (int board_type)
232 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
233 volatile memctl8260_t *memctl = &immap->im_memctl;
234 volatile uchar c = 0;
235 volatile uchar *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE) + 0x110;
238 ulong psdmr = CONFIG_SYS_PSDMR;
239 #ifdef CONFIG_SYS_LSDRAM
240 ulong lsdmr = CONFIG_SYS_LSDMR;
243 long size = CONFIG_SYS_SDRAM0_SIZE;
248 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
250 * "At system reset, initialization software must set up the
251 * programmable parameters in the memory controller banks registers
252 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
253 * system software should execute the following initialization sequence
254 * for each SDRAM device.
256 * 1. Issue a PRECHARGE-ALL-BANKS command
257 * 2. Issue eight CBR REFRESH commands
258 * 3. Issue a MODE-SET command to initialize the mode register
260 * The initial commands are executed by setting P/LSDMR[OP] and
261 * accessing the SDRAM with a single-byte transaction."
263 * The appropriate BRx/ORx registers have already been set when we
264 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
267 memctl->memc_psrt = CONFIG_SYS_PSRT;
268 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
270 memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_PREA;
273 memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_CBRR;
274 for (i = 0; i < 8; i++)
277 memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_MRW;
280 memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_NORM | PSDMR_RFEN;
283 #ifndef CONFIG_SYS_RAMBOOT
284 #ifdef CONFIG_SYS_LSDRAM
285 size += CONFIG_SYS_SDRAM1_SIZE;
286 ramaddr = (uchar *) (CONFIG_SYS_SDRAM1_BASE) + 0x8c;
287 memctl->memc_lsrt = CONFIG_SYS_LSRT;
289 memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_PREA;
292 memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_CBRR;
293 for (i = 0; i < 8; i++)
296 memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_MRW;
299 memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_NORM | PSDMR_RFEN;
301 #endif /* CONFIG_SYS_LSDRAM */
302 #endif /* CONFIG_SYS_RAMBOOT */
303 return (size * 1024 * 1024);