2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
29 /* ------------------------------------------------------------------------- */
35 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
36 extern void lxt971_no_sleep(void);
38 /* fpga configuration data - gzip compressed and generated by bin2c */
39 const unsigned char fpgadata[] =
45 * include common fpga code (for esd boards)
47 #include "../common/fpga.c"
51 int gunzip(void *, int, unsigned char *, unsigned long *);
54 #ifdef CONFIG_LCD_USED
55 /* logo bitmap data - gzip compressed and generated by bin2c */
56 unsigned char logo_bmp[] =
58 #include CFG_LCD_LOGO_NAME
62 * include common lcd code (for esd boards)
64 #include "../common/lcd.c"
66 #include CFG_LCD_HEADER_NAME
67 #endif /* CONFIG_LCD_USED */
70 int board_revision(void)
72 unsigned long cntrl0Reg;
76 * Get version of APC405 board from GPIO's
80 * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
82 cntrl0Reg = mfdcr(cntrl0);
83 mtdcr(cntrl0, cntrl0Reg | 0x03000000);
84 out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000);
85 out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000);
86 udelay(1000); /* wait some time before reading input */
87 value = in32(GPIO0_IR) & 0x00180000; /* get config bits */
90 * Restore GPIO settings
92 mtdcr(cntrl0, cntrl0Reg);
96 /* CS2==1 && CS3==1 -> version <= 1.2 */
99 /* CS2==0 && CS3==1 -> version 1.3 */
101 #if 0 /* not yet manufactured ! */
103 /* CS2==1 && CS3==0 -> version 1.4 */
106 /* CS2==0 && CS3==0 -> version 1.5 */
110 /* should not be reached! */
116 int board_early_init_f (void)
119 * First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
121 out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
122 out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */
123 out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */
124 out32(GPIO0_OR, 0); /* pull prg low */
127 * IRQ 0-15 405GP internally generated; active high; level sensitive
128 * IRQ 16 405GP internally generated; active low; level sensitive
130 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
131 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
132 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
133 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
134 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
135 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
136 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
138 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
139 mtdcr(uicer, 0x00000000); /* disable all ints */
140 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
141 mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
142 mtdcr(uictr, 0x10000000); /* set int trigger levels */
143 mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
144 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
147 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
149 #if 1 /* test-only */
150 mtebc (epcr, 0xa8400000); /* ebc always driven */
152 mtebc (epcr, 0x28400000); /* ebc in high-z */
159 /* ------------------------------------------------------------------------- */
161 int misc_init_f (void)
163 return 0; /* dummy implementation */
167 int misc_init_r (void)
169 DECLARE_GLOBAL_DATA_PTR;
171 volatile unsigned short *fpga_mode =
172 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
173 volatile unsigned short *fpga_ctrl2 =
174 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL2);
175 volatile unsigned char *duart0_mcr =
176 (unsigned char *)((ulong)DUART0_BA + 4);
177 volatile unsigned char *duart1_mcr =
178 (unsigned char *)((ulong)DUART1_BA + 4);
179 volatile unsigned short *fuji_lcdbl_pwm =
180 (unsigned short *)((ulong)0xf0100200 + 0xa0);
182 ulong len = sizeof(fpgadata);
186 unsigned long cntrl0Reg;
189 * Setup GPIO pins (CS6+CS7 as GPIO)
191 cntrl0Reg = mfdcr(cntrl0);
192 mtdcr(cntrl0, cntrl0Reg | 0x00300000);
194 dst = malloc(CFG_FPGA_MAX_SIZE);
195 if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
196 printf ("GUNZIP ERROR - must RESET board to recover\n");
197 do_reset (NULL, 0, 0, NULL);
200 status = fpga_boot(dst, len);
202 printf("\nFPGA: Booting failed ");
204 case ERROR_FPGA_PRG_INIT_LOW:
205 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
207 case ERROR_FPGA_PRG_INIT_HIGH:
208 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
210 case ERROR_FPGA_PRG_DONE:
211 printf("(Timeout: DONE not high after programming FPGA)\n ");
215 /* display infos on fpgaimage */
217 for (i=0; i<4; i++) {
219 printf("FPGA: %s\n", &(dst[index+1]));
224 for (i=20; i>0; i--) {
225 printf("Rebooting in %2d seconds \r",i);
226 for (index=0;index<1000;index++)
230 do_reset(NULL, 0, 0, NULL);
233 /* restore gpio/cs settings */
234 mtdcr(cntrl0, cntrl0Reg);
238 /* display infos on fpgaimage */
240 for (i=0; i<4; i++) {
242 printf("%s ", &(dst[index+1]));
250 * Reset FPGA via FPGA_DATA pin
252 SET_FPGA(FPGA_PRG | FPGA_CLK);
253 udelay(1000); /* wait 1ms */
254 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
255 udelay(1000); /* wait 1ms */
258 * Write board revision in FPGA
260 *fpga_ctrl2 = (*fpga_ctrl2 & 0xfff0) | (gd->board_type & 0x000f);
263 * Enable power on PS/2 interface (with reset)
265 *fpga_mode |= CFG_FPGA_CTRL_PS2_RESET;
269 *fpga_mode &= ~CFG_FPGA_CTRL_PS2_RESET;
272 * Enable interrupts in exar duart mcr[3]
278 * Init lcd interface and display logo
280 lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
281 regs_13806_640_480_16bpp,
282 sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
283 logo_bmp, sizeof(logo_bmp));
286 * Reset microcontroller and setup backlight PWM controller
288 *fpga_mode |= 0x0014;
291 *fpga_mode |= 0x001c;
292 *fuji_lcdbl_pwm = 0x00ff;
299 * Check Board Identity:
302 int checkboard (void)
304 DECLARE_GLOBAL_DATA_PTR;
306 unsigned char str[64];
307 int i = getenv_r ("serial#", str, sizeof(str));
312 puts ("### No HW ID - assuming APC405");
317 gd->board_type = board_revision();
318 printf(", Rev 1.%ld\n", gd->board_type);
321 * Disable sleep mode in LXT971
328 /* ------------------------------------------------------------------------- */
330 long int initdram (int board_type)
334 mtdcr(memcfga, mem_mb0cf);
335 val = mfdcr(memcfgd);
338 printf("\nmb0cf=%x\n", val); /* test-only */
339 printf("strap=%x\n", mfdcr(strap)); /* test-only */
342 return (4*1024*1024 << ((val & 0x000e0000) >> 17));
345 /* ------------------------------------------------------------------------- */
349 /* TODO: XXX XXX XXX */
350 printf ("test: 16 MB - ok\n");
355 /* ------------------------------------------------------------------------- */
357 #ifdef CONFIG_IDE_RESET
359 void ide_set_reset(int on)
361 volatile unsigned short *fpga_mode =
362 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
365 * Assert or deassert CompactFlash Reset Pin
367 if (on) { /* assert RESET */
368 *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
369 } else { /* release RESET */
370 *fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
374 #endif /* CONFIG_IDE_RESET */
376 /* ------------------------------------------------------------------------- */