2 * (C) Copyright 2005-2008
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
5 * (C) Copyright 2001-2003
6 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/processor.h>
33 #include <mtd/cfi_flash.h>
34 #include <asm/4xx_pci.h>
37 DECLARE_GLOBAL_DATA_PTR;
41 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
42 extern void lxt971_no_sleep(void);
44 /* fpga configuration data - gzip compressed and generated by bin2c */
45 const unsigned char fpgadata[] =
51 * include common fpga code (for esd boards)
53 #include "../common/fpga.c"
55 #ifdef CONFIG_LCD_USED
56 /* logo bitmap data - gzip compressed and generated by bin2c */
57 unsigned char logo_bmp[] =
59 #include "logo_640_480_24bpp.c"
63 * include common lcd code (for esd boards)
65 #include "../common/lcd.c"
66 #include "../common/s1d13505_640_480_16bpp.h"
67 #include "../common/s1d13806_640_480_16bpp.h"
68 #endif /* CONFIG_LCD_USED */
71 * include common auto-update code (for esd boards)
73 #include "../common/auto_update.h"
75 au_image_t au_image[] = {
76 {"preinst.img", 0, -1, AU_SCRIPT},
77 {"u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE | AU_PROTECT},
78 {"pImage", 0xfe000000, 0x00100000, AU_NOR | AU_PROTECT},
79 {"pImage.initrd", 0xfe100000, 0x00400000, AU_NOR | AU_PROTECT},
80 {"work.img", 0xfe500000, 0x01400000, AU_NOR},
81 {"data.img", 0xff900000, 0x00580000, AU_NOR},
82 {"logo.img", 0xffe80000, 0x00100000, AU_NOR | AU_PROTECT},
83 {"postinst.img", 0, 0, AU_SCRIPT},
86 int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
88 int board_revision(void)
90 unsigned long CPC0_CR0Reg;
94 * Get version of APC405 board from GPIO's
97 /* Setup GPIO pins (CS2/GPIO11, CS3/GPIO12 and CS4/GPIO13 as GPIO) */
98 CPC0_CR0Reg = mfdcr(CPC0_CR0);
99 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03800000);
100 out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x001c0000);
101 out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x001c0000);
103 /* wait some time before reading input */
106 /* get config bits */
107 value = in_be32((void*)GPIO0_IR) & 0x001c0000;
109 * Restore GPIO settings
111 mtdcr(CPC0_CR0, CPC0_CR0Reg);
115 /* CS2==1 && CS3==1 && CS4==1 -> version <= 1.2 */
118 /* CS2==0 && CS3==1 && CS4==1 -> version 1.3 */
121 /* CS2==1 && CS3==1 && CS4==0 -> version 1.6 */
124 /* CS2==1 && CS3==0 && CS4==1 -> version 1.8 */
127 /* should not be reached! */
132 int board_early_init_f (void)
135 * First pull fpga-prg pin low, to disable fpga logic
137 out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */
138 out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
139 out_be32((void*)GPIO0_OR, 0); /* pull prg low */
142 * IRQ 0-15 405GP internally generated; active high; level sensitive
143 * IRQ 16 405GP internally generated; active low; level sensitive
145 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
146 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
147 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
148 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
149 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
150 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
151 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
153 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
154 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
155 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
156 mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
157 mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
158 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0 */
159 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
162 * EBC Configuration Register: set ready timeout to 512 ebc-clks
164 mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
167 * New boards have a single 32MB flash connected to CS0
168 * instead of two 16MB flashes on CS0+1.
170 if (board_revision() >= 8) {
175 /* resize CS0 to 32MB */
176 mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP_HWREV8);
177 mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR_HWREV8);
183 int board_early_init_r(void)
185 if (gd->board_type >= 8)
186 cfi_flash_num_flash_banks = 1;
191 #define FUJI_BASE 0xf0100200
192 #define LCDBL_PWM 0xa0
193 #define LCDBL_PWMMIN 0xa4
194 #define LCDBL_PWMMAX 0xa8
196 int misc_init_r(void)
198 u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
199 u16 *fpga_ctrl2 =(u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL2);
200 u8 *duart0_mcr = (u8 *)(DUART0_BA + 4);
201 u8 *duart1_mcr = (u8 *)(DUART1_BA + 4);
203 ulong len = sizeof(fpgadata);
207 unsigned long CPC0_CR0Reg;
215 * Setup GPIO pins (CS6+CS7 as GPIO)
217 CPC0_CR0Reg = mfdcr(CPC0_CR0);
218 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
220 dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
221 if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
222 printf("GUNZIP ERROR - must RESET board to recover\n");
223 do_reset(NULL, 0, 0, NULL);
226 status = fpga_boot(dst, len);
228 printf("\nFPGA: Booting failed ");
230 case ERROR_FPGA_PRG_INIT_LOW:
232 "INIT not low after asserting PROGRAM*)\n ");
234 case ERROR_FPGA_PRG_INIT_HIGH:
236 "INIT not high after deasserting PROGRAM*)\n ");
238 case ERROR_FPGA_PRG_DONE:
240 "DONE not high after programming FPGA)\n ");
244 /* display infos on fpgaimage */
246 for (i = 0; i < 4; i++) {
248 printf("FPGA: %s\n", &(dst[index+1]));
253 for (i = 20; i > 0; i--) {
254 printf("Rebooting in %2d seconds \r",i);
255 for (index = 0; index < 1000; index++)
259 do_reset(NULL, 0, 0, NULL);
262 /* restore gpio/cs settings */
263 mtdcr(CPC0_CR0, CPC0_CR0Reg);
267 /* display infos on fpgaimage */
269 for (i = 0; i < 4; i++) {
271 printf("%s ", &(dst[index + 1]));
279 * Reset FPGA via FPGA_DATA pin
281 SET_FPGA(FPGA_PRG | FPGA_CLK);
282 udelay(1000); /* wait 1ms */
283 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
284 udelay(1000); /* wait 1ms */
287 * Write board revision in FPGA
290 (in_be16(fpga_ctrl2) & 0xfff0) | (gd->board_type & 0x000f));
293 * Enable power on PS/2 interface (with reset)
295 out_be16(fpga_mode, in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_PS2_RESET);
299 out_be16(fpga_mode, in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_PS2_RESET);
302 * Enable interrupts in exar duart mcr[3]
304 out_8(duart0_mcr, 0x08);
305 out_8(duart1_mcr, 0x08);
308 * Init lcd interface and display logo
310 str = getenv("splashimage");
312 logo_addr = (uchar *)simple_strtoul(str, NULL, 16);
313 logo_size = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
315 logo_addr = logo_bmp;
316 logo_size = sizeof(logo_bmp);
319 if (gd->board_type >= 6) {
320 result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
321 (uchar *)CONFIG_SYS_LCD_BIG_MEM,
322 regs_13505_640_480_16bpp,
323 sizeof(regs_13505_640_480_16bpp) /
324 sizeof(regs_13505_640_480_16bpp[0]),
325 logo_addr, logo_size);
327 /* retry with internal image */
328 logo_addr = logo_bmp;
329 logo_size = sizeof(logo_bmp);
330 lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
331 (uchar *)CONFIG_SYS_LCD_BIG_MEM,
332 regs_13505_640_480_16bpp,
333 sizeof(regs_13505_640_480_16bpp) /
334 sizeof(regs_13505_640_480_16bpp[0]),
335 logo_addr, logo_size);
338 result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
339 (uchar *)CONFIG_SYS_LCD_BIG_MEM,
340 regs_13806_640_480_16bpp,
341 sizeof(regs_13806_640_480_16bpp) /
342 sizeof(regs_13806_640_480_16bpp[0]),
343 logo_addr, logo_size);
345 /* retry with internal image */
346 logo_addr = logo_bmp;
347 logo_size = sizeof(logo_bmp);
348 lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
349 (uchar *)CONFIG_SYS_LCD_BIG_MEM,
350 regs_13806_640_480_16bpp,
351 sizeof(regs_13806_640_480_16bpp) /
352 sizeof(regs_13806_640_480_16bpp[0]),
353 logo_addr, logo_size);
358 * Reset microcontroller and setup backlight PWM controller
360 out_be16(fpga_mode, in_be16(fpga_mode) | 0x0014);
363 out_be16(fpga_mode, in_be16(fpga_mode) | 0x001c);
367 str = getenv("lcdbl");
369 minb = (ushort)simple_strtoul(str, &str, 16) & 0x00ff;
370 if (str && (*str=',')) {
372 maxb = (ushort)simple_strtoul(str, NULL, 16) & 0x00ff;
376 out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMIN), minb);
377 out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMAX), maxb);
379 printf("LCDBL: min=0x%02x, max=0x%02x\n", minb, maxb);
381 out_be16((u16 *)(FUJI_BASE + LCDBL_PWM), 0xff);
384 * fix environment for field updated units
386 if (getenv("altbootcmd") == NULL) {
387 setenv("usb_load", CONFIG_SYS_USB_LOAD_COMMAND);
388 setenv("usbargs", CONFIG_SYS_USB_ARGS);
389 setenv("bootcmd", CONFIG_BOOTCOMMAND);
390 setenv("usb_self", CONFIG_SYS_USB_SELF_COMMAND);
391 setenv("bootlimit", CONFIG_SYS_BOOTLIMIT);
392 setenv("altbootcmd", CONFIG_SYS_ALT_BOOTCOMMAND);
400 * Check Board Identity:
402 int checkboard (void)
405 int i = getenv_f("serial#", str, sizeof(str));
410 puts ("### No HW ID - assuming APC405");
415 gd->board_type = board_revision();
416 printf(", Rev. 1.%ld\n", gd->board_type);
421 #ifdef CONFIG_IDE_RESET
422 void ide_set_reset(int on)
424 u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
427 * Assert or deassert CompactFlash Reset Pin
431 in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
434 in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
437 #endif /* CONFIG_IDE_RESET */
442 * Disable sleep mode in LXT971
447 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
448 int usb_board_init(void)
453 int usb_board_stop(void)
460 * This is required to make some very old Linux OHCI driver
461 * work after U-Boot has used the OHCI controller.
463 pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &tmp);
464 pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (tmp | 0x1000));
466 for (i = 0; i < 100; i++)
469 pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, tmp);
473 int usb_board_init_fail(void)
478 #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */