2 * (C) Copyright 2005-2008
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
5 * (C) Copyright 2001-2003
6 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/processor.h>
33 #include <asm/4xx_pci.h>
36 DECLARE_GLOBAL_DATA_PTR;
40 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
41 extern void lxt971_no_sleep(void);
42 extern ulong flash_get_size (ulong base, int banknum);
44 int flash_banks = CONFIG_SYS_MAX_FLASH_BANKS_DETECT;
46 /* fpga configuration data - gzip compressed and generated by bin2c */
47 const unsigned char fpgadata[] =
53 * include common fpga code (for esd boards)
55 #include "../common/fpga.c"
57 #ifdef CONFIG_LCD_USED
58 /* logo bitmap data - gzip compressed and generated by bin2c */
59 unsigned char logo_bmp[] =
61 #include "logo_640_480_24bpp.c"
65 * include common lcd code (for esd boards)
67 #include "../common/lcd.c"
68 #include "../common/s1d13505_640_480_16bpp.h"
69 #include "../common/s1d13806_640_480_16bpp.h"
70 #endif /* CONFIG_LCD_USED */
73 * include common auto-update code (for esd boards)
75 #include "../common/auto_update.h"
77 au_image_t au_image[] = {
78 {"preinst.img", 0, -1, AU_SCRIPT},
79 {"u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE | AU_PROTECT},
80 {"pImage", 0xfe000000, 0x00100000, AU_NOR | AU_PROTECT},
81 {"pImage.initrd", 0xfe100000, 0x00400000, AU_NOR | AU_PROTECT},
82 {"work.img", 0xfe500000, 0x01400000, AU_NOR},
83 {"data.img", 0xff900000, 0x00580000, AU_NOR},
84 {"logo.img", 0xffe80000, 0x00100000, AU_NOR | AU_PROTECT},
85 {"postinst.img", 0, 0, AU_SCRIPT},
88 int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
90 int board_revision(void)
92 unsigned long CPC0_CR0Reg;
96 * Get version of APC405 board from GPIO's
99 /* Setup GPIO pins (CS2/GPIO11, CS3/GPIO12 and CS4/GPIO13 as GPIO) */
100 CPC0_CR0Reg = mfdcr(CPC0_CR0);
101 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03800000);
102 out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x001c0000);
103 out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x001c0000);
105 /* wait some time before reading input */
108 /* get config bits */
109 value = in_be32((void*)GPIO0_IR) & 0x001c0000;
111 * Restore GPIO settings
113 mtdcr(CPC0_CR0, CPC0_CR0Reg);
117 /* CS2==1 && CS3==1 && CS4==1 -> version <= 1.2 */
120 /* CS2==0 && CS3==1 && CS4==1 -> version 1.3 */
123 /* CS2==1 && CS3==1 && CS4==0 -> version 1.6 */
126 /* CS2==1 && CS3==0 && CS4==1 -> version 1.8 */
129 /* should not be reached! */
134 int board_early_init_f (void)
137 * First pull fpga-prg pin low, to disable fpga logic
139 out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */
140 out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
141 out_be32((void*)GPIO0_OR, 0); /* pull prg low */
144 * IRQ 0-15 405GP internally generated; active high; level sensitive
145 * IRQ 16 405GP internally generated; active low; level sensitive
147 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
148 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
149 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
150 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
151 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
152 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
153 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
155 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
156 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
157 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
158 mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
159 mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
160 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0 */
161 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
164 * EBC Configuration Register: set ready timeout to 512 ebc-clks
166 mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
169 * New boards have a single 32MB flash connected to CS0
170 * instead of two 16MB flashes on CS0+1.
172 if (board_revision() >= 8) {
177 /* resize CS0 to 32MB */
178 mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP_HWREV8);
179 mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR_HWREV8);
185 int board_early_init_r(void)
187 if (gd->board_type >= 8)
193 #define FUJI_BASE 0xf0100200
194 #define LCDBL_PWM 0xa0
195 #define LCDBL_PWMMIN 0xa4
196 #define LCDBL_PWMMAX 0xa8
198 int misc_init_r(void)
200 u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
201 u16 *fpga_ctrl2 =(u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL2);
202 u8 *duart0_mcr = (u8 *)(DUART0_BA + 4);
203 u8 *duart1_mcr = (u8 *)(DUART1_BA + 4);
205 ulong len = sizeof(fpgadata);
209 unsigned long CPC0_CR0Reg;
217 * Setup GPIO pins (CS6+CS7 as GPIO)
219 CPC0_CR0Reg = mfdcr(CPC0_CR0);
220 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
222 dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
223 if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
224 printf("GUNZIP ERROR - must RESET board to recover\n");
225 do_reset(NULL, 0, 0, NULL);
228 status = fpga_boot(dst, len);
230 printf("\nFPGA: Booting failed ");
232 case ERROR_FPGA_PRG_INIT_LOW:
234 "INIT not low after asserting PROGRAM*)\n ");
236 case ERROR_FPGA_PRG_INIT_HIGH:
238 "INIT not high after deasserting PROGRAM*)\n ");
240 case ERROR_FPGA_PRG_DONE:
242 "DONE not high after programming FPGA)\n ");
246 /* display infos on fpgaimage */
248 for (i = 0; i < 4; i++) {
250 printf("FPGA: %s\n", &(dst[index+1]));
255 for (i = 20; i > 0; i--) {
256 printf("Rebooting in %2d seconds \r",i);
257 for (index = 0; index < 1000; index++)
261 do_reset(NULL, 0, 0, NULL);
264 /* restore gpio/cs settings */
265 mtdcr(CPC0_CR0, CPC0_CR0Reg);
269 /* display infos on fpgaimage */
271 for (i = 0; i < 4; i++) {
273 printf("%s ", &(dst[index + 1]));
281 * Reset FPGA via FPGA_DATA pin
283 SET_FPGA(FPGA_PRG | FPGA_CLK);
284 udelay(1000); /* wait 1ms */
285 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
286 udelay(1000); /* wait 1ms */
289 * Write board revision in FPGA
292 (in_be16(fpga_ctrl2) & 0xfff0) | (gd->board_type & 0x000f));
295 * Enable power on PS/2 interface (with reset)
297 out_be16(fpga_mode, in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_PS2_RESET);
301 out_be16(fpga_mode, in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_PS2_RESET);
304 * Enable interrupts in exar duart mcr[3]
306 out_8(duart0_mcr, 0x08);
307 out_8(duart1_mcr, 0x08);
310 * Init lcd interface and display logo
312 str = getenv("splashimage");
314 logo_addr = (uchar *)simple_strtoul(str, NULL, 16);
315 logo_size = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
317 logo_addr = logo_bmp;
318 logo_size = sizeof(logo_bmp);
321 if (gd->board_type >= 6) {
322 result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
323 (uchar *)CONFIG_SYS_LCD_BIG_MEM,
324 regs_13505_640_480_16bpp,
325 sizeof(regs_13505_640_480_16bpp) /
326 sizeof(regs_13505_640_480_16bpp[0]),
327 logo_addr, logo_size);
329 /* retry with internal image */
330 logo_addr = logo_bmp;
331 logo_size = sizeof(logo_bmp);
332 lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
333 (uchar *)CONFIG_SYS_LCD_BIG_MEM,
334 regs_13505_640_480_16bpp,
335 sizeof(regs_13505_640_480_16bpp) /
336 sizeof(regs_13505_640_480_16bpp[0]),
337 logo_addr, logo_size);
340 result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
341 (uchar *)CONFIG_SYS_LCD_BIG_MEM,
342 regs_13806_640_480_16bpp,
343 sizeof(regs_13806_640_480_16bpp) /
344 sizeof(regs_13806_640_480_16bpp[0]),
345 logo_addr, logo_size);
347 /* retry with internal image */
348 logo_addr = logo_bmp;
349 logo_size = sizeof(logo_bmp);
350 lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
351 (uchar *)CONFIG_SYS_LCD_BIG_MEM,
352 regs_13806_640_480_16bpp,
353 sizeof(regs_13806_640_480_16bpp) /
354 sizeof(regs_13806_640_480_16bpp[0]),
355 logo_addr, logo_size);
360 * Reset microcontroller and setup backlight PWM controller
362 out_be16(fpga_mode, in_be16(fpga_mode) | 0x0014);
365 out_be16(fpga_mode, in_be16(fpga_mode) | 0x001c);
369 str = getenv("lcdbl");
371 minb = (ushort)simple_strtoul(str, &str, 16) & 0x00ff;
372 if (str && (*str=',')) {
374 maxb = (ushort)simple_strtoul(str, NULL, 16) & 0x00ff;
378 out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMIN), minb);
379 out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMAX), maxb);
381 printf("LCDBL: min=0x%02x, max=0x%02x\n", minb, maxb);
383 out_be16((u16 *)(FUJI_BASE + LCDBL_PWM), 0xff);
386 * fix environment for field updated units
388 if (getenv("altbootcmd") == NULL) {
389 setenv("usb_load", CONFIG_SYS_USB_LOAD_COMMAND);
390 setenv("usbargs", CONFIG_SYS_USB_ARGS);
391 setenv("bootcmd", CONFIG_BOOTCOMMAND);
392 setenv("usb_self", CONFIG_SYS_USB_SELF_COMMAND);
393 setenv("bootlimit", CONFIG_SYS_BOOTLIMIT);
394 setenv("altbootcmd", CONFIG_SYS_ALT_BOOTCOMMAND);
402 * Check Board Identity:
404 int checkboard (void)
407 int i = getenv_r ("serial#", str, sizeof(str));
412 puts ("### No HW ID - assuming APC405");
417 gd->board_type = board_revision();
418 printf(", Rev. 1.%ld\n", gd->board_type);
423 #ifdef CONFIG_IDE_RESET
424 void ide_set_reset(int on)
426 u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
429 * Assert or deassert CompactFlash Reset Pin
433 in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
436 in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
439 #endif /* CONFIG_IDE_RESET */
444 * Disable sleep mode in LXT971
449 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
450 int usb_board_init(void)
455 int usb_board_stop(void)
462 * This is required to make some very old Linux OHCI driver
463 * work after U-Boot has used the OHCI controller.
465 pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &tmp);
466 pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (tmp | 0x1000));
468 for (i = 0; i < 100; i++)
471 pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, tmp);
475 int usb_board_init_fail(void)
480 #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */