2 * (C) Copyright 2005-2008
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
5 * (C) Copyright 2001-2003
6 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
8 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/processor.h>
17 #include <mtd/cfi_flash.h>
18 #include <asm/4xx_pci.h>
22 DECLARE_GLOBAL_DATA_PTR;
26 extern void lxt971_no_sleep(void);
28 /* fpga configuration data - gzip compressed and generated by bin2c */
29 const unsigned char fpgadata[] =
35 * include common fpga code (for esd boards)
37 #include "../common/fpga.c"
39 #ifdef CONFIG_LCD_USED
40 /* logo bitmap data - gzip compressed and generated by bin2c */
41 unsigned char logo_bmp[] =
43 #include "logo_640_480_24bpp.c"
47 * include common lcd code (for esd boards)
49 #include "../common/lcd.c"
50 #include "../common/s1d13505_640_480_16bpp.h"
51 #include "../common/s1d13806_640_480_16bpp.h"
52 #endif /* CONFIG_LCD_USED */
55 * include common auto-update code (for esd boards)
57 #include "../common/auto_update.h"
59 au_image_t au_image[] = {
60 {"preinst.img", 0, -1, AU_SCRIPT},
61 {"u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE | AU_PROTECT},
62 {"pImage", 0xfe000000, 0x00100000, AU_NOR | AU_PROTECT},
63 {"pImage.initrd", 0xfe100000, 0x00400000, AU_NOR | AU_PROTECT},
64 {"work.img", 0xfe500000, 0x01400000, AU_NOR},
65 {"data.img", 0xff900000, 0x00580000, AU_NOR},
66 {"logo.img", 0xffe80000, 0x00100000, AU_NOR | AU_PROTECT},
67 {"postinst.img", 0, 0, AU_SCRIPT},
70 int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
72 int board_revision(void)
74 unsigned long CPC0_CR0Reg;
78 * Get version of APC405 board from GPIO's
81 /* Setup GPIO pins (CS2/GPIO11, CS3/GPIO12 and CS4/GPIO13 as GPIO) */
82 CPC0_CR0Reg = mfdcr(CPC0_CR0);
83 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03800000);
84 out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x001c0000);
85 out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x001c0000);
87 /* wait some time before reading input */
91 value = in_be32((void*)GPIO0_IR) & 0x001c0000;
93 * Restore GPIO settings
95 mtdcr(CPC0_CR0, CPC0_CR0Reg);
99 /* CS2==1 && CS3==1 && CS4==1 -> version <= 1.2 */
102 /* CS2==0 && CS3==1 && CS4==1 -> version 1.3 */
105 /* CS2==1 && CS3==1 && CS4==0 -> version 1.6 */
108 /* CS2==1 && CS3==0 && CS4==1 -> version 1.8 */
111 /* should not be reached! */
116 int board_early_init_f (void)
119 * First pull fpga-prg pin low, to disable fpga logic
121 out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */
122 out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
123 out_be32((void*)GPIO0_OR, 0); /* pull prg low */
126 * IRQ 0-15 405GP internally generated; active high; level sensitive
127 * IRQ 16 405GP internally generated; active low; level sensitive
129 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
130 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
131 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
132 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
133 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
134 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
135 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
137 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
138 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
139 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
140 mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
141 mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
142 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0 */
143 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
146 * EBC Configuration Register: set ready timeout to 512 ebc-clks
148 mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
151 * New boards have a single 32MB flash connected to CS0
152 * instead of two 16MB flashes on CS0+1.
154 if (board_revision() >= 8) {
159 /* resize CS0 to 32MB */
160 mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP_HWREV8);
161 mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR_HWREV8);
167 int board_early_init_r(void)
169 if (gd->board_type >= 8)
170 cfi_flash_num_flash_banks = 1;
175 #define FUJI_BASE 0xf0100200
176 #define LCDBL_PWM 0xa0
177 #define LCDBL_PWMMIN 0xa4
178 #define LCDBL_PWMMAX 0xa8
180 int misc_init_r(void)
182 u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
183 u16 *fpga_ctrl2 =(u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL2);
184 u8 *duart0_mcr = (u8 *)(DUART0_BA + 4);
185 u8 *duart1_mcr = (u8 *)(DUART1_BA + 4);
187 ulong len = sizeof(fpgadata);
191 unsigned long CPC0_CR0Reg;
199 * Setup GPIO pins (CS6+CS7 as GPIO)
201 CPC0_CR0Reg = mfdcr(CPC0_CR0);
202 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
204 dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
205 if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
206 printf("GUNZIP ERROR - must RESET board to recover\n");
207 do_reset(NULL, 0, 0, NULL);
210 status = fpga_boot(dst, len);
212 printf("\nFPGA: Booting failed ");
214 case ERROR_FPGA_PRG_INIT_LOW:
216 "INIT not low after asserting PROGRAM*)\n ");
218 case ERROR_FPGA_PRG_INIT_HIGH:
220 "INIT not high after deasserting PROGRAM*)\n ");
222 case ERROR_FPGA_PRG_DONE:
224 "DONE not high after programming FPGA)\n ");
228 /* display infos on fpgaimage */
230 for (i = 0; i < 4; i++) {
232 printf("FPGA: %s\n", &(dst[index+1]));
237 for (i = 20; i > 0; i--) {
238 printf("Rebooting in %2d seconds \r",i);
239 for (index = 0; index < 1000; index++)
243 do_reset(NULL, 0, 0, NULL);
246 /* restore gpio/cs settings */
247 mtdcr(CPC0_CR0, CPC0_CR0Reg);
251 /* display infos on fpgaimage */
253 for (i = 0; i < 4; i++) {
255 printf("%s ", &(dst[index + 1]));
263 * Reset FPGA via FPGA_DATA pin
265 SET_FPGA(FPGA_PRG | FPGA_CLK);
266 udelay(1000); /* wait 1ms */
267 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
268 udelay(1000); /* wait 1ms */
271 * Write board revision in FPGA
274 (in_be16(fpga_ctrl2) & 0xfff0) | (gd->board_type & 0x000f));
277 * Enable power on PS/2 interface (with reset)
279 out_be16(fpga_mode, in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_PS2_RESET);
283 out_be16(fpga_mode, in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_PS2_RESET);
286 * Enable interrupts in exar duart mcr[3]
288 out_8(duart0_mcr, 0x08);
289 out_8(duart1_mcr, 0x08);
292 * Init lcd interface and display logo
294 str = getenv("splashimage");
296 logo_addr = (uchar *)simple_strtoul(str, NULL, 16);
297 logo_size = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
299 logo_addr = logo_bmp;
300 logo_size = sizeof(logo_bmp);
303 if (gd->board_type >= 6) {
304 result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
305 (uchar *)CONFIG_SYS_LCD_BIG_MEM,
306 regs_13505_640_480_16bpp,
307 sizeof(regs_13505_640_480_16bpp) /
308 sizeof(regs_13505_640_480_16bpp[0]),
309 logo_addr, logo_size);
311 /* retry with internal image */
312 logo_addr = logo_bmp;
313 logo_size = sizeof(logo_bmp);
314 lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
315 (uchar *)CONFIG_SYS_LCD_BIG_MEM,
316 regs_13505_640_480_16bpp,
317 sizeof(regs_13505_640_480_16bpp) /
318 sizeof(regs_13505_640_480_16bpp[0]),
319 logo_addr, logo_size);
322 result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
323 (uchar *)CONFIG_SYS_LCD_BIG_MEM,
324 regs_13806_640_480_16bpp,
325 sizeof(regs_13806_640_480_16bpp) /
326 sizeof(regs_13806_640_480_16bpp[0]),
327 logo_addr, logo_size);
329 /* retry with internal image */
330 logo_addr = logo_bmp;
331 logo_size = sizeof(logo_bmp);
332 lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
333 (uchar *)CONFIG_SYS_LCD_BIG_MEM,
334 regs_13806_640_480_16bpp,
335 sizeof(regs_13806_640_480_16bpp) /
336 sizeof(regs_13806_640_480_16bpp[0]),
337 logo_addr, logo_size);
342 * Reset microcontroller and setup backlight PWM controller
344 out_be16(fpga_mode, in_be16(fpga_mode) | 0x0014);
347 out_be16(fpga_mode, in_be16(fpga_mode) | 0x001c);
351 str = getenv("lcdbl");
353 minb = (ushort)simple_strtoul(str, &str, 16) & 0x00ff;
354 if (str && (*str=',')) {
356 maxb = (ushort)simple_strtoul(str, NULL, 16) & 0x00ff;
360 out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMIN), minb);
361 out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMAX), maxb);
363 printf("LCDBL: min=0x%02x, max=0x%02x\n", minb, maxb);
365 out_be16((u16 *)(FUJI_BASE + LCDBL_PWM), 0xff);
368 * fix environment for field updated units
370 if (getenv("altbootcmd") == NULL) {
371 setenv("usb_load", CONFIG_SYS_USB_LOAD_COMMAND);
372 setenv("usbargs", CONFIG_SYS_USB_ARGS);
373 setenv("bootcmd", CONFIG_BOOTCOMMAND);
374 setenv("usb_self", CONFIG_SYS_USB_SELF_COMMAND);
375 setenv("bootlimit", CONFIG_SYS_BOOTLIMIT);
376 setenv("altbootcmd", CONFIG_SYS_ALT_BOOTCOMMAND);
384 * Check Board Identity:
386 int checkboard (void)
389 int i = getenv_f("serial#", str, sizeof(str));
394 puts ("### No HW ID - assuming APC405");
399 gd->board_type = board_revision();
400 printf(", Rev. 1.%ld\n", gd->board_type);
405 #ifdef CONFIG_IDE_RESET
406 void ide_set_reset(int on)
408 u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
411 * Assert or deassert CompactFlash Reset Pin
415 in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
418 in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
421 #endif /* CONFIG_IDE_RESET */
426 * Disable sleep mode in LXT971
431 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
432 int board_usb_init(int index, enum board_usb_init_type init)
437 int usb_board_stop(void)
444 * This is required to make some very old Linux OHCI driver
445 * work after U-Boot has used the OHCI controller.
447 pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &tmp);
448 pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (tmp | 0x1000));
450 for (i = 0; i < 100; i++)
453 pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, tmp);
457 int board_usb_cleanup(int index, enum board_usb_init_type init)
459 return usb_board_stop();
461 #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */