3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/processor.h>
14 DECLARE_GLOBAL_DATA_PTR;
16 /* ------------------------------------------------------------------------- */
22 /* fpga configuration data */
23 const unsigned char fpgadata[] = {
28 * include common fpga code (for esd boards)
30 #include "../common/fpga.c"
33 int board_early_init_f (void)
35 unsigned long CPC0_CR0Reg;
42 CPC0_CR0Reg = mfdcr (CPC0_CR0) & 0xf0001fff;
43 CPC0_CR0Reg |= 0x0070f000;
44 mtdcr (CPC0_CR0, CPC0_CR0Reg);
47 /* set up serial port with default baudrate */
49 gd->baudrate = CONFIG_BAUDRATE;
57 status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
59 /* booting FPGA failed */
61 /* set up serial port with default baudrate */
63 gd->baudrate = CONFIG_BAUDRATE;
67 printf ("\nFPGA: Booting failed ");
69 case ERROR_FPGA_PRG_INIT_LOW:
70 printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
72 case ERROR_FPGA_PRG_INIT_HIGH:
73 printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
75 case ERROR_FPGA_PRG_DONE:
76 printf ("(Timeout: DONE not high after programming FPGA)\n ");
80 /* display infos on fpgaimage */
82 for (i = 0; i < 4; i++) {
83 len = fpgadata[index];
84 printf ("FPGA: %s\n", &(fpgadata[index + 1]));
89 for (i = 20; i > 0; i--) {
90 printf ("Rebooting in %2d seconds \r", i);
91 for (index = 0; index < 1000; index++)
95 do_reset (NULL, 0, 0, NULL);
99 * Setup port pins for normal operation
101 out_be32 ((void *)GPIO0_ODR, 0x00000000); /* no open drain pins */
102 out_be32 ((void *)GPIO0_TCR, 0x07038100); /* setup for output */
103 out_be32 ((void *)GPIO0_OR, 0x07030100); /* set output pins to high (default) */
106 * IRQ 0-15 405GP internally generated; active high; level sensitive
107 * IRQ 16 405GP internally generated; active low; level sensitive
109 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
110 * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
111 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
112 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
113 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
114 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
115 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
117 mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
118 mtdcr (UIC0ER, 0x00000000); /* disable all ints */
119 mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
120 mtdcr (UIC0PR, 0xFFFFFF81); /* set int polarities */
121 mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
122 mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
123 mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
129 /* ------------------------------------------------------------------------- */
132 * Check Board Identity:
135 int checkboard (void)
140 int i = getenv_f("serial#", str, sizeof (str));
144 if (!i || strncmp (str, "CANBT", 5)) {
145 puts ("### No HW ID - assuming CANBT\n");
153 /* display infos on fpgaimage */
155 for (i = 0; i < 4; i++) {
156 len = fpgadata[index];
157 printf ("%s ", &(fpgadata[index + 1]));