3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
30 DECLARE_GLOBAL_DATA_PTR;
33 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
36 /* ------------------------------------------------------------------------- */
42 /* fpga configuration data */
43 const unsigned char fpgadata[] = {
48 * include common fpga code (for esd boards)
50 #include "../common/fpga.c"
53 int board_early_init_f (void)
55 unsigned long CPC0_CR0Reg;
62 CPC0_CR0Reg = mfdcr (CPC0_CR0) & 0xf0001fff;
63 CPC0_CR0Reg |= 0x0070f000;
64 mtdcr (CPC0_CR0, CPC0_CR0Reg);
67 /* set up serial port with default baudrate */
69 gd->baudrate = CONFIG_BAUDRATE;
77 status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
79 /* booting FPGA failed */
81 /* set up serial port with default baudrate */
83 gd->baudrate = CONFIG_BAUDRATE;
87 printf ("\nFPGA: Booting failed ");
89 case ERROR_FPGA_PRG_INIT_LOW:
90 printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
92 case ERROR_FPGA_PRG_INIT_HIGH:
93 printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
95 case ERROR_FPGA_PRG_DONE:
96 printf ("(Timeout: DONE not high after programming FPGA)\n ");
100 /* display infos on fpgaimage */
102 for (i = 0; i < 4; i++) {
103 len = fpgadata[index];
104 printf ("FPGA: %s\n", &(fpgadata[index + 1]));
109 for (i = 20; i > 0; i--) {
110 printf ("Rebooting in %2d seconds \r", i);
111 for (index = 0; index < 1000; index++)
115 do_reset (NULL, 0, 0, NULL);
119 * Setup port pins for normal operation
121 out_be32 ((void *)GPIO0_ODR, 0x00000000); /* no open drain pins */
122 out_be32 ((void *)GPIO0_TCR, 0x07038100); /* setup for output */
123 out_be32 ((void *)GPIO0_OR, 0x07030100); /* set output pins to high (default) */
126 * IRQ 0-15 405GP internally generated; active high; level sensitive
127 * IRQ 16 405GP internally generated; active low; level sensitive
129 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
130 * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
131 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
132 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
133 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
134 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
135 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
137 mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
138 mtdcr (UIC0ER, 0x00000000); /* disable all ints */
139 mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
140 mtdcr (UIC0PR, 0xFFFFFF81); /* set int polarities */
141 mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
142 mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
143 mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
149 /* ------------------------------------------------------------------------- */
152 * Check Board Identity:
155 int checkboard (void)
160 int i = getenv_r ("serial#", str, sizeof (str));
164 if (!i || strncmp (str, "CANBT", 5)) {
165 puts ("### No HW ID - assuming CANBT\n");
173 /* display infos on fpgaimage */
175 for (i = 0; i < 4; i++) {
176 len = fpgadata[index];
177 printf ("%s ", &(fpgadata[index + 1]));