2 * (C) Copyright 2001-2004
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
4 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/processor.h>
14 /* ------------------------------------------------------------------------- */
17 #define DBG(x...) printf(x)
24 #ifdef CONFIG_SYS_FPGA_PRG
25 # define FPGA_PRG CONFIG_SYS_FPGA_PRG /* FPGA program pin (ppc output) */
26 # define FPGA_CLK CONFIG_SYS_FPGA_CLK /* FPGA clk pin (ppc output) */
27 # define FPGA_DATA CONFIG_SYS_FPGA_DATA /* FPGA data pin (ppc output) */
28 # define FPGA_DONE CONFIG_SYS_FPGA_DONE /* FPGA done pin (ppc input) */
29 # define FPGA_INIT CONFIG_SYS_FPGA_INIT /* FPGA init pin (ppc input) */
31 # define FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
32 # define FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
33 # define FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
34 # define FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */
35 # define FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */
38 #define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */
39 #define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */
40 #define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */
43 # define SET_FPGA(data) out_be32((void *)GPIO0_OR, data)
46 #ifdef FPGA_PROG_ACTIVE_HIGH
47 # define FPGA_PRG_LOW FPGA_PRG
48 # define FPGA_PRG_HIGH 0
50 # define FPGA_PRG_LOW 0
51 # define FPGA_PRG_HIGH FPGA_PRG
54 #define FPGA_CLK_LOW 0
55 #define FPGA_CLK_HIGH FPGA_CLK
57 #define FPGA_DATA_LOW 0
58 #define FPGA_DATA_HIGH FPGA_DATA
60 #define FPGA_WRITE_1 { \
61 SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set clock to 0 */ \
62 SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set data to 1 */ \
63 SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set clock to 1 */ \
64 SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1 */
66 #define FPGA_WRITE_0 { \
67 SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set clock to 0 */ \
68 SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_LOW); /* set data to 0 */ \
69 SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_LOW); /* set clock to 1 */ \
70 SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1 */
72 #ifndef FPGA_DONE_STATE
73 # define FPGA_DONE_STATE (in_be32((void *)GPIO0_IR) & FPGA_DONE)
75 #ifndef FPGA_INIT_STATE
76 # define FPGA_INIT_STATE (in_be32((void *)GPIO0_IR) & FPGA_INIT)
80 static int fpga_boot (const unsigned char *fpgadata, int size)
86 #ifdef CONFIG_SYS_FPGA_SPARTAN2
92 /* display infos on fpgaimage */
94 for (i = 0; i < 4; i++) {
95 len = fpgadata[index];
96 DBG ("FPGA: %s\n", &(fpgadata[index + 1]));
100 #ifdef CONFIG_SYS_FPGA_SPARTAN2
101 /* search for preamble 0xFFFFFFFF */
103 if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff)
104 && (fpgadata[index + 2] == 0xff)
105 && (fpgadata[index + 3] == 0xff))
106 break; /* preamble found */
111 /* search for preamble 0xFF2X */
112 for (index = 0; index < size - 1; index++) {
113 if ((fpgadata[index] == 0xff)
114 && ((fpgadata[index + 1] & 0xf0) == 0x30))
120 DBG ("FPGA: configdata starts at position 0x%x\n", index);
121 DBG ("FPGA: length of fpga-data %d\n", size - index);
124 * Setup port pins for fpga programming
127 out_be32 ((void *)GPIO0_ODR, 0x00000000); /* no open drain pins */
128 /* setup for output */
129 out_be32 ((void *)GPIO0_TCR,
130 in_be32 ((void *)GPIO0_TCR) |
131 FPGA_PRG | FPGA_CLK | FPGA_DATA);
133 SET_FPGA (FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set pins to high */
135 DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
136 DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
139 * Init fpga by asserting and deasserting PROGRAM*
141 SET_FPGA (FPGA_PRG_LOW | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set prog active */
143 /* Wait for FPGA init line low */
145 while (FPGA_INIT_STATE) {
146 udelay (1000); /* wait 1ms */
147 /* Check for timeout - 100us max, so use 3ms */
149 DBG ("FPGA: Booting failed!\n");
150 return ERROR_FPGA_PRG_INIT_LOW;
154 DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
155 DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
157 /* deassert PROGRAM* */
158 SET_FPGA (FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set prog inactive */
160 /* Wait for FPGA end of init period . */
162 while (!(FPGA_INIT_STATE)) {
163 udelay (1000); /* wait 1ms */
164 /* Check for timeout */
166 DBG ("FPGA: Booting failed!\n");
167 return ERROR_FPGA_PRG_INIT_HIGH;
171 DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
172 DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
174 DBG ("write configuration data into fpga\n");
175 /* write configuration-data into fpga... */
177 #ifdef CONFIG_SYS_FPGA_SPARTAN2
179 * Load uncompressed image into fpga
181 for (i = index; i < size; i++) {
183 for (j = 0; j < 8; j++) {
184 if ((b & 0x80) == 0x80) {
213 ** Code 1 .. maxOnes : n '1's followed by '0'
214 ** maxOnes + 1 .. maxOnes + 1 : n - 1 '1's no '0'
215 ** maxOnes + 2 .. 254 : n - (maxOnes + 2) '0's followed by '1'
219 for (i = index; i < size; i++) {
221 if ((b >= 1) && (b <= MAX_ONES)) {
222 for (bit = 0; bit < b; bit++) {
226 } else if (b == (MAX_ONES + 1)) {
227 for (bit = 1; bit < b; bit++) {
230 } else if ((b >= (MAX_ONES + 2)) && (b <= 254)) {
231 for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) {
235 } else if (b == 255) {
241 DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
242 DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
245 * Check if fpga's DONE signal - correctly booted ?
248 /* Wait for FPGA end of programming period . */
250 while (!(FPGA_DONE_STATE)) {
251 udelay (1000); /* wait 1ms */
252 /* Check for timeout */
254 DBG ("FPGA: Booting failed!\n");
255 return ERROR_FPGA_PRG_DONE;
259 DBG ("FPGA: Booting successful!\n");