2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <fdt_support.h>
11 #include <asm/processor.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 extern void __ft_board_setup(void *blob, bd_t *bd);
24 /* fpga configuration data - generated by bin2cc */
25 const unsigned char fpgadata[] =
27 #if defined(CONFIG_CPCI405_VER2)
28 # include "fpgadata_cpci4052.c"
33 * include common fpga code (for esd boards)
35 #include "../common/fpga.c"
38 int cpci405_version(void);
39 void lxt971_no_sleep(void);
41 int board_early_init_f(void)
43 #ifndef CONFIG_CPCI405_VER2
49 /* set up serial port with default baudrate */
51 gd->baudrate = CONFIG_BAUDRATE;
57 * First pull fpga-prg pin low,
58 * to disable fpga logic (on version 2 board)
60 out_be32((void *)GPIO0_ODR, 0x00000000); /* no open drain pins */
61 out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
62 out_be32((void *)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
63 out_be32((void *)GPIO0_OR, 0); /* pull prg low */
68 #ifndef CONFIG_CPCI405_VER2
69 if (cpci405_version() == 1) {
70 status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata));
72 /* booting FPGA failed */
74 /* set up serial port with default baudrate */
76 gd->baudrate = CONFIG_BAUDRATE;
80 printf("\nFPGA: Booting failed ");
82 case ERROR_FPGA_PRG_INIT_LOW:
83 printf("(Timeout: INIT not low after "
84 "asserting PROGRAM*)\n ");
86 case ERROR_FPGA_PRG_INIT_HIGH:
87 printf("(Timeout: INIT not high after "
88 "deasserting PROGRAM*)\n ");
90 case ERROR_FPGA_PRG_DONE:
91 printf("(Timeout: DONE not high after "
92 "programming FPGA)\n ");
96 /* display infos on fpgaimage */
98 for (i = 0; i < 4; i++) {
99 len = fpgadata[index];
100 printf("FPGA: %s\n", &(fpgadata[index + 1]));
105 for (i = 20; i > 0; i--) {
106 printf("Rebooting in %2d seconds \r",i);
107 for (index = 0; index < 1000; index++)
111 do_reset(NULL, 0, 0, NULL);
114 #endif /* !CONFIG_CPCI405_VER2 */
117 * IRQ 0-15 405GP internally generated; active high; level sensitive
118 * IRQ 16 405GP internally generated; active low; level sensitive
120 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
121 * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052); active low; level sens.
122 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
123 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
124 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
125 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
126 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
128 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
129 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
130 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
131 #if defined(CONFIG_CPCI405_6U)
132 if (cpci405_version() == 3) {
133 mtdcr(UIC0PR, 0xFFFFFF99); /* set int polarities */
135 mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
138 mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
140 mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
141 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,
142 * INT0 highest priority */
143 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
150 #if defined(CONFIG_CPCI405_VER2)
151 return 0; /* no, board is cpci405 */
153 if ((in_8((void*)0xf0000400) == 0x00) &&
154 (in_8((void*)0xf0000401) == 0x01))
155 return 0; /* no, board is cpci405 */
157 return -1; /* yes, board is cterm-m2 */
161 int cpci405_host(void)
163 if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN)
164 return -1; /* yes, board is cpci405 host */
166 return 0; /* no, board is cpci405 adapter */
169 int cpci405_version(void)
171 unsigned long CPC0_CR0Reg;
175 * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
177 CPC0_CR0Reg = mfdcr(CPC0_CR0);
178 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000);
179 out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
180 out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
181 udelay(1000); /* wait some time before reading input */
182 value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */
185 * Restore GPIO settings
187 mtdcr(CPC0_CR0, CPC0_CR0Reg);
191 /* CS2==1 && CS3==1 -> version 1 */
194 /* CS2==0 && CS3==1 -> version 2 */
197 /* CS2==1 && CS3==0 -> version 3 or 6U board */
200 /* CS2==0 && CS3==0 -> version 4 */
203 /* should not be reached! */
208 int misc_init_r (void)
210 unsigned long CPC0_CR0Reg;
212 /* adjust flash start and offset */
213 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
214 gd->bd->bi_flashoffset = 0;
216 #if defined(CONFIG_CPCI405_VER2)
219 ulong len = sizeof(fpgadata);
225 * On CPCI-405 version 2 the environment is saved in eeprom!
226 * FPGA can be gzip compressed (malloc) and booted this late.
228 if (cpci405_version() >= 2) {
230 * Setup GPIO pins (CS6+CS7 as GPIO)
232 CPC0_CR0Reg = mfdcr(CPC0_CR0);
233 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
235 dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
236 if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
237 (uchar *)fpgadata, &len) != 0) {
238 printf("GUNZIP ERROR - must RESET board to recover\n");
239 do_reset(NULL, 0, 0, NULL);
242 status = fpga_boot(dst, len);
244 printf("\nFPGA: Booting failed ");
246 case ERROR_FPGA_PRG_INIT_LOW:
247 printf("(Timeout: INIT not low after "
248 "asserting PROGRAM*)\n ");
250 case ERROR_FPGA_PRG_INIT_HIGH:
251 printf("(Timeout: INIT not high after "
252 "deasserting PROGRAM*)\n ");
254 case ERROR_FPGA_PRG_DONE:
255 printf("(Timeout: DONE not high after "
256 "programming FPGA)\n ");
260 /* display infos on fpgaimage */
262 for (i = 0; i < 4; i++) {
264 printf("FPGA: %s\n", &(dst[index + 1]));
269 for (i = 20; i > 0; i--) {
270 printf("Rebooting in %2d seconds \r", i);
271 for (index = 0; index < 1000; index++)
275 do_reset(NULL, 0, 0, NULL);
278 /* restore gpio/cs settings */
279 mtdcr(CPC0_CR0, CPC0_CR0Reg);
283 /* display infos on fpgaimage */
285 for (i = 0; i < 4; i++) {
287 printf("%s ", &(dst[index + 1]));
295 * Reset FPGA via FPGA_DATA pin
297 SET_FPGA(FPGA_PRG | FPGA_CLK);
298 udelay(1000); /* wait 1ms */
299 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
300 udelay(1000); /* wait 1ms */
302 #if defined(CONFIG_CPCI405_6U)
303 #error HIER GETH ES WEITER MIT IO ACCESSORS
304 if (cpci405_version() == 3) {
306 * Enable outputs in fpga on version 3 board
308 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
309 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
310 CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT);
315 out_8((void*)CONFIG_SYS_LED_ADDR, 0x00);
318 * Reset external DUART
320 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
321 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
322 CONFIG_SYS_FPGA_MODE_DUART_RESET);
324 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
325 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
326 ~CONFIG_SYS_FPGA_MODE_DUART_RESET);
331 puts("\n*** U-Boot Version does not match Board Version!\n");
332 puts("*** CPCI-405 Version 1.x detected!\n");
333 puts("*** Please use correct U-Boot version "
334 "(CPCI405 instead of CPCI4052)!\n\n");
337 #else /* CONFIG_CPCI405_VER2 */
338 if (cpci405_version() >= 2) {
339 puts("\n*** U-Boot Version does not match Board Version!\n");
340 puts("*** CPCI-405 Board Version 2.x detected!\n");
341 puts("*** Please use correct U-Boot version "
342 "(CPCI4052 instead of CPCI405)!\n\n");
344 #endif /* CONFIG_CPCI405_VER2 */
347 * Select cts (and not dsr) on uart1
349 CPC0_CR0Reg = mfdcr(CPC0_CR0);
350 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
356 * Check Board Identity:
361 #ifndef CONFIG_CPCI405_VER2
366 int i = getenv_f("serial#", str, sizeof(str));
372 puts("### No HW ID - assuming CPCI405");
376 ver = cpci405_version();
377 printf(" (Ver %d.x, ", ver);
383 * Read board-id and save in env-variable
385 sprintf(str, "%d", *(unsigned char *)0xf0000400);
386 setenv("boardid", str);
387 printf("CTERM-M2 - Id=%s)", str);
390 puts("PCI Host Version)");
392 puts("PCI Adapter Version)");
395 #ifndef CONFIG_CPCI405_VER2
398 /* display infos on fpgaimage */
400 for (i = 0; i < 4; i++) {
401 len = fpgadata[index];
402 printf("%s ", &(fpgadata[index + 1]));
413 #if defined(CONFIG_LXT971_NO_SLEEP)
416 * Disable sleep mode in LXT971
422 #if defined(CONFIG_CPCI405_VER2) && defined (CONFIG_IDE_RESET)
423 void ide_set_reset(int on)
426 * Assert or deassert CompactFlash Reset Pin
428 if (on) { /* assert RESET */
429 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
430 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
431 ~CONFIG_SYS_FPGA_MODE_CF_RESET);
432 } else { /* release RESET */
433 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
434 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
435 CONFIG_SYS_FPGA_MODE_CF_RESET);
439 #endif /* CONFIG_IDE_RESET && CONFIG_CPCI405_VER2 */
441 #if defined(CONFIG_PCI)
442 void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
444 unsigned char int_line = 0xff;
447 * Write pci interrupt line register (cpci405 specific)
449 switch (PCI_DEV(dev) & 0x03) {
464 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
467 int pci_pre_init(struct pci_controller *hose)
469 hose->fixup_irq = cpci405_pci_fixup_irq;
472 #endif /* defined(CONFIG_PCI) */
474 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
475 int ft_board_setup(void *blob, bd_t *bd)
479 __ft_board_setup(blob, bd);
482 * Disable PCI in adapter mode.
484 if (!cpci405_host()) {
485 rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status",
486 "disabled", sizeof("disabled"), 1);
488 printf("Unable to update property status in PCI node, "
496 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */