3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
29 long int fixed_sdram( void );
31 int board_pre_init (void)
35 /*--------------------------------------------------------------------
36 * Setup the external bus controller/chip selects
37 *-------------------------------------------------------------------*/
38 mtdcr( ebccfga, xbcfg );
39 reg = mfdcr( ebccfgd );
40 mtdcr( ebccfgd, reg | 0x04000000 ); /* Set ATC */
42 mtebc( pb0ap, 0x92015480 ); /* FLASH/SRAM */
43 mtebc( pb0cr, 0xFF87A000 ); /* BAS=0xff8 8MB R/W 16-bit */
44 /* test-only: other regs still missing... */
46 /*--------------------------------------------------------------------
47 * Setup the interrupt controller polarities, triggers, etc.
48 *-------------------------------------------------------------------*/
49 mtdcr( uic0sr, 0xffffffff ); /* clear all */
50 mtdcr( uic0er, 0x00000000 ); /* disable all */
51 mtdcr( uic0cr, 0x00000009 ); /* SMI & UIC1 crit are critical */
52 mtdcr( uic0pr, 0xfffffe13 ); /* per ref-board manual */
53 mtdcr( uic0tr, 0x01c00008 ); /* per ref-board manual */
54 mtdcr( uic0vr, 0x00000001 ); /* int31 highest, base=0x000 */
55 mtdcr( uic0sr, 0xffffffff ); /* clear all */
57 mtdcr( uic1sr, 0xffffffff ); /* clear all */
58 mtdcr( uic1er, 0x00000000 ); /* disable all */
59 mtdcr( uic1cr, 0x00000000 ); /* all non-critical */
60 mtdcr( uic1pr, 0xffffe0ff ); /* per ref-board manual */
61 mtdcr( uic1tr, 0x00ffc000 ); /* per ref-board manual */
62 mtdcr( uic1vr, 0x00000001 ); /* int31 highest, base=0x000 */
63 mtdcr( uic1sr, 0xffffffff ); /* clear all */
73 get_sys_info(&sysinfo);
75 printf("Board: esd CPCI-440\n");
76 printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz/1000000);
77 printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor/1000000);
78 printf("\tPLB: %lu MHz\n", sysinfo.freqPLB/1000000);
79 printf("\tOPB: %lu MHz\n", sysinfo.freqOPB/1000000);
80 printf("\tEPB: %lu MHz\n", sysinfo.freqEPB/1000000);
85 long int initdram (int board_type)
89 dram_size = fixed_sdram();
94 /*************************************************************************
95 * fixed sdram init -- doesn't use serial presence detect.
97 * Assumes: 64 MB, non-ECC, non-registered
100 ************************************************************************/
101 long int fixed_sdram( void )
105 /*--------------------------------------------------------------------
107 *------------------------------------------------------------------*/
108 mtsdram( mem_uabba, 0x00000000 ); /* ubba=0 (default) */
109 mtsdram( mem_slio, 0x00000000 ); /* rdre=0 wrre=0 rarw=0 */
110 mtsdram( mem_devopt,0x00000000 ); /* dll=0 ds=0 (normal) */
111 mtsdram( mem_wddctr,0x40000000 ); /* wrcp=0 dcd=0 */
112 mtsdram( mem_clktr, 0x40000000 ); /* clkp=1 (90 deg wr) dcdt=0 */
114 /*--------------------------------------------------------------------
115 * Setup for board-specific specific mem
116 *------------------------------------------------------------------*/
118 * Following for CAS Latency = 2.5 @ 133 MHz PLB
120 mtsdram( mem_b0cr, 0x00082001 );/* SDBA=0x000, 64MB, Mode 2, enabled*/
121 mtsdram( mem_tr0, 0x410a4012 );/* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
123 mtsdram( mem_tr1, 0x8080082f );/* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
124 mtsdram( mem_rtr, 0x08200000 );/* Rate 15.625 ns @ 133 MHz PLB */
125 mtsdram( mem_cfg1, 0x00000000 );/* Self-refresh exit, disable PM */
126 udelay( 400 ); /* Delay 200 usecs (min) */
128 /*--------------------------------------------------------------------
129 * Enable the controller, then wait for DCEN to complete
130 *------------------------------------------------------------------*/
131 mtsdram( mem_cfg0, 0x86000000 );/* DCEN=1, PMUD=1, 64-bit */
134 mfsdram( mem_mcsts, reg );
135 if( reg & 0x80000000 )
139 return( 64 * 1024 * 1024 ); /* 64 MB */