3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com
24 * modifications for the cpci750 by reinhard.arlt@esd-electronics.com
28 * cpci750.c - main board support/init for the esd cpci750.
34 #include "../../Marvell/include/memory.h"
35 #include "../../Marvell/include/pci.h"
36 #include "../../Marvell/include/mv_gen_reg.h"
50 #endif /* of CONFIG_PCI */
58 static char show_config_tab[][15] = {{"PCI0DLL_2 "}, /* 31 */
59 {"PCI0DLL_1 "}, /* 30 */
60 {"PCI0DLL_0 "}, /* 29 */
61 {"PCI1DLL_2 "}, /* 28 */
62 {"PCI1DLL_1 "}, /* 27 */
63 {"PCI1DLL_0 "}, /* 26 */
64 {"BbEP2En "}, /* 25 */
65 {"SDRAMRdDataDel"}, /* 24 */
66 {"SDRAMRdDel "}, /* 23 */
67 {"SDRAMSync "}, /* 22 */
68 {"SDRAMPipeSel_1"}, /* 21 */
69 {"SDRAMPipeSel_0"}, /* 20 */
70 {"SDRAMAddDel "}, /* 19 */
71 {"SDRAMClkSel "}, /* 18 */
72 {"Reserved(1!) "}, /* 17 */
74 {"BootCSWidth_1 "}, /* 15 */
75 {"BootCSWidth_0 "}, /* 14 */
76 {"PCI1PadsCal "}, /* 13 */
77 {"PCI0PadsCal "}, /* 12 */
78 {"MultiMVId_1 "}, /* 11 */
79 {"MultiMVId_0 "}, /* 10 */
80 {"MultiGTEn "}, /* 09 */
81 {"Int60xArb "}, /* 08 */
82 {"CPUBusConfig_1"}, /* 07 */
83 {"CPUBusConfig_0"}, /* 06 */
84 {"DefIntSpc "}, /* 05 */
86 {"SROMAdd_1 "}, /* 03 */
87 {"SROMAdd_0 "}, /* 02 */
88 {"DRAMPadCal "}, /* 01 */
89 {"SInitEn "}, /* 00 */
100 {"JTAGCalBy "}, /* 21 */
101 {"GB2Sel "}, /* 20 */
102 {"GB1Sel "}, /* 19 */
103 {"DRAMPLL_MDiv_5"}, /* 18 */
104 {"DRAMPLL_MDiv_4"}, /* 17 */
105 {"DRAMPLL_MDiv_3"}, /* 16 */
106 {"DRAMPLL_MDiv_2"}, /* 15 */
107 {"DRAMPLL_MDiv_1"}, /* 14 */
108 {"DRAMPLL_MDiv_0"}, /* 13 */
109 {"GB0Sel "}, /* 12 */
110 {"DRAMPLLPU "}, /* 11 */
111 {"DRAMPLL_HIKVCO"}, /* 10 */
112 {"DRAMPLLNP "}, /* 09 */
113 {"DRAMPLL_NDiv_7"}, /* 08 */
114 {"DRAMPLL_NDiv_6"}, /* 07 */
115 {"CPUPadCal "}, /* 06 */
116 {"DRAMPLL_NDiv_5"}, /* 05 */
117 {"DRAMPLL_NDiv_4"}, /* 04 */
118 {"DRAMPLL_NDiv_3"}, /* 03 */
119 {"DRAMPLL_NDiv_2"}, /* 02 */
120 {"DRAMPLL_NDiv_1"}, /* 01 */
121 {"DRAMPLL_NDiv_0"}}; /* 00 */
123 extern void flush_data_cache (void);
124 extern void invalidate_l1_instruction_cache (void);
125 extern flash_info_t flash_info[];
127 /* ------------------------------------------------------------------------- */
129 /* this is the current GT register space location */
130 /* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
132 /* Unfortunately, we cant change it while we are in flash, so we initialize it
133 * to the "final" value. This means that any debug_led calls before
134 * board_early_init_f wont work right (like in cpu_init_f).
135 * See also my_remap_gt_regs below. (NTL)
138 void board_prebootm_init (void);
139 unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
140 int display_mem_map (void);
142 /* ------------------------------------------------------------------------- */
145 * This is a version of the GT register space remapping function that
146 * doesn't touch globals (meaning, it's ok to run from flash.)
148 * Unfortunately, this has the side effect that a writable
149 * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
152 void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
156 /* check and see if it's already moved */
158 /* original ppcboot 1.1.6 source
160 temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
161 if ((temp & 0xffff) == new_loc >> 20)
164 temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
165 0xffff0000) | (new_loc >> 20);
167 out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
169 while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
170 original ppcboot 1.1.6 source end */
172 temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
173 if ((temp & 0xffff) == new_loc >> 16)
176 temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
177 0xffff0000) | (new_loc >> 16);
179 out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
181 while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
186 static void gt_pci_config (void)
189 unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, FuncNum 10:8, RegNum 7:2 */
191 /* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's
192 * config registers by writing ones to the bus and device.
193 * We then update the Virtual register with the correct value for the bus and device.
195 if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
196 GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
198 GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
200 GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
201 GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
202 (stat & 0xffff0000) | CFG_PCI_IDSEL);
205 if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
206 GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
207 GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
209 GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
210 GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
211 (stat & 0xffff0000) | CFG_PCI_IDSEL);
215 PCI_MASTER_ENABLE (0, SELF);
216 PCI_MASTER_ENABLE (1, SELF);
218 /* Enable PCI0/1 Mem0 and IO 0 disable all others */
219 GT_REG_READ (BASE_ADDR_ENABLE, &stat);
220 stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1
223 stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
224 GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
226 /* ronen- add write to pci remap registers for 64460.
227 in 64360 when writing to pci base go and overide remap automaticaly,
228 in 64460 it doesn't */
229 GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_SPACE >> 16);
230 GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_SPACE_PCI >> 16);
231 GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16);
233 GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16);
234 GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16);
235 GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16);
237 GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_SPACE >> 16);
238 GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_SPACE_PCI >> 16);
239 GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16);
241 GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16);
242 GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16);
243 GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16);
245 /* PCI interface settings */
246 /* Timeout set to retry forever */
247 GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
248 GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
250 /* ronen - enable only CS0 and Internal reg!! */
251 GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
252 GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
254 /*ronen update the pci internal registers base address.*/
256 for (stat = 0; stat <= PCI_HOST1; stat++)
257 pciWriteConfigReg (stat,
258 PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
265 /* Setup CPU interface paramaters */
266 static void gt_cpu_config (void)
268 cpu_t cpu = get_cpu_type ();
271 /* cpu configuration register */
272 tmp = GTREGREAD (CPU_CONFIGURATION);
274 /* set the SINGLE_CPU bit see MV64360 P.399 */
275 #ifndef CFG_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */
276 tmp |= CPU_CONF_SINGLE_CPU;
279 tmp &= ~CPU_CONF_AACK_DELAY_2;
281 tmp |= CPU_CONF_DP_VALID;
282 tmp |= CPU_CONF_AP_VALID;
284 tmp |= CPU_CONF_PIPELINE;
286 GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */
288 /* CPU master control register */
289 tmp = GTREGREAD (CPU_MASTER_CONTROL);
291 tmp |= CPU_MAST_CTL_ARB_EN;
293 if ((cpu == CPU_7400) ||
294 (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
296 tmp |= CPU_MAST_CTL_CLEAN_BLK;
297 tmp |= CPU_MAST_CTL_FLUSH_BLK;
300 /* cleanblock must be cleared for CPUs
301 * that do not support this command (603e, 750)
303 tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
304 tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
306 GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
310 * board_early_init_f.
312 * set up gal. device mappings, etc.
314 int board_early_init_f (void)
318 * set up the GT the way the kernel wants it
319 * the call to move the GT register space will obviously
320 * fail if it has already been done, but we're going to assume
321 * that if it's not at the power-on location, it's where we put
322 * it last time. (huber)
325 my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS);
327 /* No PCI in first release of Port To_do: enable it. */
331 /* mask all external interrupt sources */
332 GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
333 GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
335 GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
336 GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
337 /* --------------------- */
338 GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
339 GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
340 GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
341 GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
342 /* does not exist in MV6436x
343 GT_REG_WRITE(CPU_INT_0_MASK, 0);
344 GT_REG_WRITE(CPU_INT_1_MASK, 0);
345 GT_REG_WRITE(CPU_INT_2_MASK, 0);
346 GT_REG_WRITE(CPU_INT_3_MASK, 0);
347 --------------------- */
350 /* ----- DEVICE BUS SETTINGS ------ */
357 * 3 - Flash checked 32Bit Intel Strata
358 * boot - BootCS checked 8Bit 29LV040B
363 * the dual 7450 module requires burst access to the boot
364 * device, so the serial rom copies the boot device to the
365 * on-board sram on the eval board, and updates the correct
366 * registers to boot from the sram. (device0)
369 memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
370 memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE);
371 memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE);
372 memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE);
375 /* configure device timing */
376 GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR);
377 GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR);
378 GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR);
379 GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_DEV3_PAR);
381 #ifdef CFG_32BIT_BOOT_PAR /* set port parameters for Flash device module access */
382 /* detect if we are booting from the 32 bit flash */
383 if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
384 /* 32 bit boot flash */
385 GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR);
386 GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
389 /* 8 bit boot flash */
390 GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR);
391 GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
394 /* 8 bit boot flash only */
395 /* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/
402 GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0);
403 GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1);
404 GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2);
405 GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3);
407 GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
415 /* various things to do after relocation */
430 /* disable the dcache and MMU */
433 if (flash_info[3].size < CFG_FLASH_INCREMENT) {
434 unsigned int flash_offset;
437 flash_offset = CFG_FLASH_INCREMENT - flash_info[3].size;
438 for (l = 0; l < CFG_MAX_FLASH_SECT; l++) {
439 if (flash_info[3].start[l] != 0) {
440 flash_info[3].start[l] += flash_offset;
443 flash_protect (FLAG_PROTECT_SET,
445 CFG_MONITOR_BASE + monitor_flash_len - 1,
451 void after_reloc (ulong dest_addr, gd_t * gd)
454 memoryMapDeviceSpace (BOOT_DEVICE, CFG_BOOT_SPACE, CFG_BOOT_SIZE);
457 /* now, jump to the main ppcboot board init code */
458 board_init_r (gd, dest_addr);
462 /* ------------------------------------------------------------------------- */
465 * Check Board Identity:
467 * right now, assume borad type. (there is just one...after all)
470 int checkboard (void)
474 printf ("BOARD: %s\n", CFG_BOARD_NAME);
478 /* utility functions */
479 void debug_led (int led, int mode)
483 int display_mem_map (void)
486 unsigned int base, size, width;
489 printf ("SD (DDR) RAM\n");
490 for (i = 0; i <= BANK3; i++) {
491 base = memoryGetBankBaseAddress (i);
492 size = memoryGetBankSize (i);
494 printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
495 i, base, size >> 20);
499 /* CPU's PCI windows */
500 for (i = 0; i <= PCI_HOST1; i++) {
501 printf ("\nCPU's PCI %d windows\n", i);
502 base = pciGetSpaceBase (i, PCI_IO);
503 size = pciGetSpaceSize (i, PCI_IO);
504 printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base,
509 /*ronen currently only first PCI MEM is used 3 */ ;
511 base = pciGetSpaceBase (i, j);
512 size = pciGetSpaceSize (i, j);
513 printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20);
516 #endif /* of CONFIG_PCI */
518 printf ("\nDEVICES\n");
519 for (i = 0; i <= DEVICE3; i++) {
520 base = memoryGetDeviceBaseAddress (i);
521 size = memoryGetDeviceSize (i);
522 width = memoryGetDeviceWidth (i) * 8;
523 printf ("DEV %d: base - 0x%08x size - %dM bytes\twidth - %d bits", i, base, size >> 20, width);
525 printf ("\t- FLASH\n");
527 printf ("\t- FLASH\n");
529 printf ("\t- FLASH\n");
531 printf ("\t- RTC/REGS/CAN\n");
535 base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */
536 size = memoryGetDeviceSize (BOOT_DEVICE);
537 width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
538 printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\t- FLASH\n",
539 base, size >> 20, width);
543 /* DRAM check routines copied from gw8260 */
545 #if defined (CFG_DRAM_TEST)
547 /*********************************************************************/
548 /* NAME: move64() - moves a double word (64-bit) */
551 /* this function performs a double word move from the data at */
552 /* the source pointer to the location at the destination pointer. */
555 /* unsigned long long *src - pointer to data to move */
558 /* unsigned long long *dest - pointer to locate to move data */
563 /* RESTRICTIONS/LIMITATIONS: */
564 /* May cloober fr0. */
566 /*********************************************************************/
567 static void move64 (unsigned long long *src, unsigned long long *dest)
569 asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
570 "stfd 0, 0(4)" /* *dest = fpr0 */
571 : : : "fr0"); /* Clobbers fr0 */
576 #if defined (CFG_DRAM_TEST_DATA)
578 unsigned long long pattern[] = {
579 0xaaaaaaaaaaaaaaaaLL,
580 0xccccccccccccccccLL,
581 0xf0f0f0f0f0f0f0f0LL,
582 0xff00ff00ff00ff00LL,
583 0xffff0000ffff0000LL,
584 0xffffffff00000000LL,
585 0x00000000ffffffffLL,
586 0x0000ffff0000ffffLL,
587 0x00ff00ff00ff00ffLL,
588 0x0f0f0f0f0f0f0f0fLL,
589 0x3333333333333333LL,
590 0x5555555555555555LL,
593 /*********************************************************************/
594 /* NAME: mem_test_data() - test data lines for shorts and opens */
597 /* Tests data lines for shorts and opens by forcing adjacent data */
598 /* to opposite states. Because the data lines could be routed in */
599 /* an arbitrary manner the must ensure test patterns ensure that */
600 /* every case is tested. By using the following series of binary */
601 /* patterns every combination of adjacent bits is test regardless */
604 /* ...101010101010101010101010 */
605 /* ...110011001100110011001100 */
606 /* ...111100001111000011110000 */
607 /* ...111111110000000011111111 */
609 /* Carrying this out, gives us six hex patterns as follows: */
611 /* 0xaaaaaaaaaaaaaaaa */
612 /* 0xcccccccccccccccc */
613 /* 0xf0f0f0f0f0f0f0f0 */
614 /* 0xff00ff00ff00ff00 */
615 /* 0xffff0000ffff0000 */
616 /* 0xffffffff00000000 */
618 /* The number test patterns will always be given by: */
620 /* log(base 2)(number data bits) = log2 (64) = 6 */
622 /* To test for short and opens to other signals on our boards. we */
624 /* test with the 1's complemnt of the paterns as well. */
627 /* Displays failing test pattern */
630 /* 0 - Passed test */
631 /* 1 - Failed test */
633 /* RESTRICTIONS/LIMITATIONS: */
634 /* Assumes only one one SDRAM bank */
636 /*********************************************************************/
637 int mem_test_data (void)
639 unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
640 unsigned long long temp64 = 0;
641 int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
645 for (i = 0; i < num_patterns; i++) {
646 move64 (&(pattern[i]), pmem);
647 move64 (pmem, &temp64);
649 /* hi = (temp64>>32) & 0xffffffff; */
650 /* lo = temp64 & 0xffffffff; */
651 /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
653 hi = (pattern[i] >> 32) & 0xffffffff;
654 lo = pattern[i] & 0xffffffff;
655 /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */
657 if (temp64 != pattern[i]) {
658 printf ("\n Data Test Failed, pattern 0x%08x%08x",
666 #endif /* CFG_DRAM_TEST_DATA */
668 #if defined (CFG_DRAM_TEST_ADDRESS)
669 /*********************************************************************/
670 /* NAME: mem_test_address() - test address lines */
673 /* This function performs a test to verify that each word im */
674 /* memory is uniquly addressable. The test sequence is as follows: */
676 /* 1) write the address of each word to each word. */
677 /* 2) verify that each location equals its address */
680 /* Displays failing test pattern and address */
683 /* 0 - Passed test */
684 /* 1 - Failed test */
686 /* RESTRICTIONS/LIMITATIONS: */
689 /*********************************************************************/
690 int mem_test_address (void)
692 volatile unsigned int *pmem =
693 (volatile unsigned int *) CFG_MEMTEST_START;
694 const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4;
697 /* write address to each location */
698 for (i = 0; i < size; i++) {
702 /* verify each loaction */
703 for (i = 0; i < size; i++) {
705 printf ("\n Address Test Failed at 0x%x", i);
711 #endif /* CFG_DRAM_TEST_ADDRESS */
713 #if defined (CFG_DRAM_TEST_WALK)
714 /*********************************************************************/
715 /* NAME: mem_march() - memory march */
718 /* Marches up through memory. At each location verifies rmask if */
719 /* read = 1. At each location write wmask if write = 1. Displays */
720 /* failing address and pattern. */
723 /* volatile unsigned long long * base - start address of test */
724 /* unsigned int size - number of dwords(64-bit) to test */
725 /* unsigned long long rmask - read verify mask */
726 /* unsigned long long wmask - wrtie verify mask */
727 /* short read - verifies rmask if read = 1 */
728 /* short write - writes wmask if write = 1 */
731 /* Displays failing test pattern and address */
734 /* 0 - Passed test */
735 /* 1 - Failed test */
737 /* RESTRICTIONS/LIMITATIONS: */
740 /*********************************************************************/
741 int mem_march (volatile unsigned long long *base,
743 unsigned long long rmask,
744 unsigned long long wmask, short read, short write)
747 unsigned long long temp = 0;
748 unsigned int hitemp, lotemp, himask, lomask;
750 for (i = 0; i < size; i++) {
752 /* temp = base[i]; */
753 move64 ((unsigned long long *) &(base[i]), &temp);
755 hitemp = (temp >> 32) & 0xffffffff;
756 lotemp = temp & 0xffffffff;
757 himask = (rmask >> 32) & 0xffffffff;
758 lomask = rmask & 0xffffffff;
760 printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
765 /* base[i] = wmask; */
766 move64 (&wmask, (unsigned long long *) &(base[i]));
771 #endif /* CFG_DRAM_TEST_WALK */
773 /*********************************************************************/
774 /* NAME: mem_test_walk() - a simple walking ones test */
777 /* Performs a walking ones through entire physical memory. The */
778 /* test uses as series of memory marches, mem_march(), to verify */
779 /* and write the test patterns to memory. The test sequence is as */
781 /* 1) march writing 0000...0001 */
782 /* 2) march verifying 0000...0001 , writing 0000...0010 */
783 /* 3) repeat step 2 shifting masks left 1 bit each time unitl */
784 /* the write mask equals 1000...0000 */
785 /* 4) march verifying 1000...0000 */
786 /* The test fails if any of the memory marches return a failure. */
789 /* Displays which pass on the memory test is executing */
792 /* 0 - Passed test */
793 /* 1 - Failed test */
795 /* RESTRICTIONS/LIMITATIONS: */
798 /*********************************************************************/
799 int mem_test_walk (void)
801 unsigned long long mask;
802 volatile unsigned long long *pmem =
803 (volatile unsigned long long *) CFG_MEMTEST_START;
804 const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8;
810 printf ("Initial Pass");
811 mem_march (pmem, size, 0x0, 0x1, 0, 1);
813 printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
816 printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
818 for (i = 0; i < 63; i++) {
819 printf ("Pass %2d", i + 2);
820 if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
821 /*printf("mask: 0x%x, pass: %d, ", mask, i); */
825 printf ("\b\b\b\b\b\b\b");
828 printf ("Last Pass");
829 if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
830 /* printf("mask: 0x%x", mask); */
833 printf ("\b\b\b\b\b\b\b\b\b");
835 printf ("\b\b\b\b\b\b\b\b\b");
840 /*********************************************************************/
841 /* NAME: testdram() - calls any enabled memory tests */
844 /* Runs memory tests if the environment test variables are set to */
848 /* testdramdata - If set to 'y', data test is run. */
849 /* testdramaddress - If set to 'y', address test is run. */
850 /* testdramwalk - If set to 'y', walking ones test is run */
856 /* 0 - Passed test */
857 /* 1 - Failed test */
859 /* RESTRICTIONS/LIMITATIONS: */
862 /*********************************************************************/
870 #ifdef CFG_DRAM_TEST_DATA
871 s = getenv ("testdramdata");
872 rundata = (s && (*s == 'y')) ? 1 : 0;
874 #ifdef CFG_DRAM_TEST_ADDRESS
875 s = getenv ("testdramaddress");
876 runaddress = (s && (*s == 'y')) ? 1 : 0;
878 #ifdef CFG_DRAM_TEST_WALK
879 s = getenv ("testdramwalk");
880 runwalk = (s && (*s == 'y')) ? 1 : 0;
883 if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
884 printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END);
886 #ifdef CFG_DRAM_TEST_DATA
888 printf ("Test DATA ... ");
889 if (mem_test_data () == 1) {
890 printf ("failed \n");
896 #ifdef CFG_DRAM_TEST_ADDRESS
897 if (runaddress == 1) {
898 printf ("Test ADDRESS ... ");
899 if (mem_test_address () == 1) {
900 printf ("failed \n");
906 #ifdef CFG_DRAM_TEST_WALK
908 printf ("Test WALKING ONEs ... ");
909 if (mem_test_walk () == 1) {
910 printf ("failed \n");
916 if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
922 #endif /* CFG_DRAM_TEST */
924 /* ronen - the below functions are used by the bootm function */
925 /* - we map the base register to fbe00000 (same mapping as in the LSP) */
926 /* - we turn off the RX gig dmas - to prevent the dma from overunning */
927 /* the kernel data areas. */
928 /* - we diable and invalidate the icache and dcache. */
929 void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
933 temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
934 if ((temp & 0xffff) == new_loc >> 16)
937 temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
938 0xffff0000) | (new_loc >> 16);
940 out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
942 while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
944 (INTERNAL_SPACE_DECODE)))))
949 void board_prebootm_init ()
952 /* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */
953 GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16);
955 /* Stop GigE Rx DMA engines */
956 GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00);
957 /* GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00); */
958 /* GV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00); */
960 /* Relocate MV64360 internal regs */
961 my_remap_gt_regs_bootm (CFG_GT_REGS, CFG_DFL_GT_REGS);
964 invalidate_l1_instruction_cache ();
969 int do_show_config(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
971 unsigned int reset_sample_low;
972 unsigned int reset_sample_high;
973 unsigned int l, l1, l2;
975 GT_REG_READ(0x3c4, &reset_sample_low);
976 GT_REG_READ(0x3d4, &reset_sample_high);
977 printf("Reset configuration 0x%08x 0x%08x\n", reset_sample_low, reset_sample_high);
980 for (l=0; l<63; l++) {
981 if (show_config_tab[l][0] != 0) {
982 printf("%14s:%1x ", show_config_tab[l],
983 ((reset_sample_low >> (31 - (l & 0x1f)))) & 0x01);
991 reset_sample_low = reset_sample_high;
999 show_config, 1, 1, do_show_config,
1000 "show_config - Show Marvell strapping register\n",
1001 "Show Marvell strapping register (ResetSampleLow ResetSampleHigh)\n"