3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
7 * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com
8 * modifications for the cpci750 by reinhard.arlt@esd-electronics.com
12 * cpci750.c - main board support/init for the esd cpci750.
18 #include "../../Marvell/include/memory.h"
19 #include "../../Marvell/include/pci.h"
20 #include "../../Marvell/include/mv_gen_reg.h"
34 #endif /* of CONFIG_PCI */
42 static char show_config_tab[][15] = {{"PCI0DLL_2 "}, /* 31 */
43 {"PCI0DLL_1 "}, /* 30 */
44 {"PCI0DLL_0 "}, /* 29 */
45 {"PCI1DLL_2 "}, /* 28 */
46 {"PCI1DLL_1 "}, /* 27 */
47 {"PCI1DLL_0 "}, /* 26 */
48 {"BbEP2En "}, /* 25 */
49 {"SDRAMRdDataDel"}, /* 24 */
50 {"SDRAMRdDel "}, /* 23 */
51 {"SDRAMSync "}, /* 22 */
52 {"SDRAMPipeSel_1"}, /* 21 */
53 {"SDRAMPipeSel_0"}, /* 20 */
54 {"SDRAMAddDel "}, /* 19 */
55 {"SDRAMClkSel "}, /* 18 */
56 {"Reserved(1!) "}, /* 17 */
58 {"BootCSWidth_1 "}, /* 15 */
59 {"BootCSWidth_0 "}, /* 14 */
60 {"PCI1PadsCal "}, /* 13 */
61 {"PCI0PadsCal "}, /* 12 */
62 {"MultiMVId_1 "}, /* 11 */
63 {"MultiMVId_0 "}, /* 10 */
64 {"MultiGTEn "}, /* 09 */
65 {"Int60xArb "}, /* 08 */
66 {"CPUBusConfig_1"}, /* 07 */
67 {"CPUBusConfig_0"}, /* 06 */
68 {"DefIntSpc "}, /* 05 */
70 {"SROMAdd_1 "}, /* 03 */
71 {"SROMAdd_0 "}, /* 02 */
72 {"DRAMPadCal "}, /* 01 */
73 {"SInitEn "}, /* 00 */
84 {"JTAGCalBy "}, /* 21 */
87 {"DRAMPLL_MDiv_5"}, /* 18 */
88 {"DRAMPLL_MDiv_4"}, /* 17 */
89 {"DRAMPLL_MDiv_3"}, /* 16 */
90 {"DRAMPLL_MDiv_2"}, /* 15 */
91 {"DRAMPLL_MDiv_1"}, /* 14 */
92 {"DRAMPLL_MDiv_0"}, /* 13 */
94 {"DRAMPLLPU "}, /* 11 */
95 {"DRAMPLL_HIKVCO"}, /* 10 */
96 {"DRAMPLLNP "}, /* 09 */
97 {"DRAMPLL_NDiv_7"}, /* 08 */
98 {"DRAMPLL_NDiv_6"}, /* 07 */
99 {"CPUPadCal "}, /* 06 */
100 {"DRAMPLL_NDiv_5"}, /* 05 */
101 {"DRAMPLL_NDiv_4"}, /* 04 */
102 {"DRAMPLL_NDiv_3"}, /* 03 */
103 {"DRAMPLL_NDiv_2"}, /* 02 */
104 {"DRAMPLL_NDiv_1"}, /* 01 */
105 {"DRAMPLL_NDiv_0"}}; /* 00 */
107 extern flash_info_t flash_info[];
109 extern int do_bootvx (cmd_tbl_t *, int, int, char *[]);
111 /* ------------------------------------------------------------------------- */
113 /* this is the current GT register space location */
114 /* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
116 /* Unfortunately, we cant change it while we are in flash, so we initialize it
117 * to the "final" value. This means that any debug_led calls before
118 * board_early_init_f wont work right (like in cpu_init_f).
119 * See also my_remap_gt_regs below. (NTL)
122 void board_prebootm_init (void);
123 unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
124 int display_mem_map (void);
127 * Skip video initialization on slave variant.
128 * This function will overwrite the weak default in cfb_console.c
130 int board_video_skip(void)
132 return CPCI750_SLAVE_TEST;
135 /* ------------------------------------------------------------------------- */
138 * This is a version of the GT register space remapping function that
139 * doesn't touch globals (meaning, it's ok to run from flash.)
141 * Unfortunately, this has the side effect that a writable
142 * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
145 void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
149 /* check and see if it's already moved */
151 /* original ppcboot 1.1.6 source
153 temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
154 if ((temp & 0xffff) == new_loc >> 20)
157 temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
158 0xffff0000) | (new_loc >> 20);
160 out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
162 while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
163 original ppcboot 1.1.6 source end */
165 temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
166 if ((temp & 0xffff) == new_loc >> 16)
169 temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
170 0xffff0000) | (new_loc >> 16);
172 out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
174 while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
179 static void gt_pci_config (void)
183 unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, FuncNum 10:8, RegNum 7:2 */
185 /* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's
186 * config registers by writing ones to the bus and device.
187 * We then update the Virtual register with the correct value for the bus and device.
189 if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
190 GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
192 GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
194 GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
195 GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
196 (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
199 if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
200 GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
201 GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
203 GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
204 GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
205 (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
209 PCI_MASTER_ENABLE (0, SELF);
210 PCI_MASTER_ENABLE (1, SELF);
212 /* Enable PCI0/1 Mem0 and IO 0 disable all others */
213 GT_REG_READ (BASE_ADDR_ENABLE, &stat);
214 stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1
217 stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
218 GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
220 /* ronen- add write to pci remap registers for 64460.
221 in 64360 when writing to pci base go and overide remap automaticaly,
222 in 64460 it doesn't */
223 GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_SPACE >> 16);
224 GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_SPACE_PCI >> 16);
225 GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
227 GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
228 GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
229 GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
231 GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_SPACE >> 16);
232 GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_SPACE_PCI >> 16);
233 GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
235 GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
236 GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
237 GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
239 /* PCI interface settings */
240 /* Timeout set to retry forever */
241 GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
242 GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
244 /* ronen - enable only CS0 and Internal reg!! */
245 GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
246 GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
248 /*ronen update the pci internal registers base address.*/
250 for (stat = 0; stat <= PCI_HOST1; stat++) {
251 data = pciReadConfigReg(stat,
252 PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
254 data = (data & 0x0f) | CONFIG_SYS_GT_REGS;
255 pciWriteConfigReg (stat,
256 PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
264 /* Setup CPU interface paramaters */
265 static void gt_cpu_config (void)
267 cpu_t cpu = get_cpu_type ();
270 /* cpu configuration register */
271 tmp = GTREGREAD (CPU_CONFIGURATION);
273 /* set the SINGLE_CPU bit see MV64360 P.399 */
274 #ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */
275 tmp |= CPU_CONF_SINGLE_CPU;
278 tmp &= ~CPU_CONF_AACK_DELAY_2;
280 tmp |= CPU_CONF_DP_VALID;
281 tmp |= CPU_CONF_AP_VALID;
283 tmp |= CPU_CONF_PIPELINE;
285 GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */
287 /* CPU master control register */
288 tmp = GTREGREAD (CPU_MASTER_CONTROL);
290 tmp |= CPU_MAST_CTL_ARB_EN;
292 if ((cpu == CPU_7400) ||
293 (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
295 tmp |= CPU_MAST_CTL_CLEAN_BLK;
296 tmp |= CPU_MAST_CTL_FLUSH_BLK;
299 /* cleanblock must be cleared for CPUs
300 * that do not support this command (603e, 750)
302 tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
303 tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
305 GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
309 * board_early_init_f.
311 * set up gal. device mappings, etc.
313 int board_early_init_f (void)
317 * set up the GT the way the kernel wants it
318 * the call to move the GT register space will obviously
319 * fail if it has already been done, but we're going to assume
320 * that if it's not at the power-on location, it's where we put
321 * it last time. (huber)
324 my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
326 /* No PCI in first release of Port To_do: enable it. */
330 /* mask all external interrupt sources */
331 GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
332 GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
334 GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
335 GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
336 /* --------------------- */
337 GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
338 GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
339 GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
340 GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
341 /* does not exist in MV6436x
342 GT_REG_WRITE(CPU_INT_0_MASK, 0);
343 GT_REG_WRITE(CPU_INT_1_MASK, 0);
344 GT_REG_WRITE(CPU_INT_2_MASK, 0);
345 GT_REG_WRITE(CPU_INT_3_MASK, 0);
346 --------------------- */
349 /* ----- DEVICE BUS SETTINGS ------ */
356 * 3 - Flash checked 32Bit Intel Strata
357 * boot - BootCS checked 8Bit 29LV040B
362 * the dual 7450 module requires burst access to the boot
363 * device, so the serial rom copies the boot device to the
364 * on-board sram on the eval board, and updates the correct
365 * registers to boot from the sram. (device0)
368 memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
369 memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
370 memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
371 memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
374 /* configure device timing */
375 GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
376 GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
377 GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
378 GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_DEV3_PAR);
380 #ifdef CONFIG_SYS_32BIT_BOOT_PAR /* set port parameters for Flash device module access */
381 /* detect if we are booting from the 32 bit flash */
382 if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
383 /* 32 bit boot flash */
384 GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
385 GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
386 CONFIG_SYS_32BIT_BOOT_PAR);
388 /* 8 bit boot flash */
389 GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
390 GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
393 /* 8 bit boot flash only */
394 /* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/
401 GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
402 GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
403 GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
404 GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
406 GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
414 /* various things to do after relocation */
429 /* disable the dcache and MMU */
432 if (flash_info[3].size < CONFIG_SYS_FLASH_INCREMENT) {
433 unsigned int flash_offset;
436 flash_offset = CONFIG_SYS_FLASH_INCREMENT - flash_info[3].size;
437 for (l = 0; l < CONFIG_SYS_MAX_FLASH_SECT; l++) {
438 if (flash_info[3].start[l] != 0) {
439 flash_info[3].start[l] += flash_offset;
442 flash_protect (FLAG_PROTECT_SET,
443 CONFIG_SYS_MONITOR_BASE,
444 CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
450 void after_reloc (ulong dest_addr, gd_t * gd)
452 memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE,
453 CONFIG_SYS_BOOT_SIZE);
456 GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
457 GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
459 /* now, jump to the main ppcboot board init code */
460 board_init_r (gd, dest_addr);
464 /* ------------------------------------------------------------------------- */
467 * Check Board Identity:
469 * right now, assume borad type. (there is just one...after all)
472 int checkboard (void)
476 printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
480 /* utility functions */
481 void debug_led (int led, int mode)
485 int display_mem_map (void)
488 unsigned int base, size, width;
491 printf ("SD (DDR) RAM\n");
492 for (i = 0; i <= BANK3; i++) {
493 base = memoryGetBankBaseAddress (i);
494 size = memoryGetBankSize (i);
496 printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
497 i, base, size >> 20);
501 /* CPU's PCI windows */
502 for (i = 0; i <= PCI_HOST1; i++) {
503 printf ("\nCPU's PCI %d windows\n", i);
504 base = pciGetSpaceBase (i, PCI_IO);
505 size = pciGetSpaceSize (i, PCI_IO);
506 printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base,
511 /*ronen currently only first PCI MEM is used 3 */ ;
513 base = pciGetSpaceBase (i, j);
514 size = pciGetSpaceSize (i, j);
515 printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20);
518 #endif /* of CONFIG_PCI */
520 printf ("\nDEVICES\n");
521 for (i = 0; i <= DEVICE3; i++) {
522 base = memoryGetDeviceBaseAddress (i);
523 size = memoryGetDeviceSize (i);
524 width = memoryGetDeviceWidth (i) * 8;
525 printf ("DEV %d: base - 0x%08x size - %dM bytes\twidth - %d bits", i, base, size >> 20, width);
527 printf ("\t- FLASH\n");
529 printf ("\t- FLASH\n");
531 printf ("\t- FLASH\n");
533 printf ("\t- RTC/REGS/CAN\n");
537 base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */
538 size = memoryGetDeviceSize (BOOT_DEVICE);
539 width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
540 printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\t- FLASH\n",
541 base, size >> 20, width);
546 * Command loadpci: wait for signal from host and boot image.
548 int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
550 volatile unsigned int *ptr;
555 char str[] = "\\|/-";
564 puts("\nWaiting for image from pci host -");
567 * Wait for host to write the start address
569 while (*ptr == 0xffffffff) {
571 if (!(count % 100)) {
573 putc(0x08); /* backspace */
574 putc(str[count2 % 4]);
577 /* Abort if ctrl-c was pressed */
586 sprintf(addr, "%08x", *ptr);
587 printf("\nBooting Image at addr 0x%s ...\n", addr);
588 setenv("loadaddr", addr);
590 switch (ptr[1] == 0) {
593 * Boot image via bootm
595 local_args[0] = argv[0];
596 local_args[1] = NULL;
597 status = do_bootm (cmdtp, 0, 1, local_args);
601 * Boot image via bootvx
603 local_args[0] = argv[0];
604 local_args[1] = NULL;
605 status = do_bootvx (cmdtp, 0, 1, local_args);
613 loadpci, 1, 1, do_loadpci,
614 "loadpci - Wait for pci-image and boot it\n",
618 /* DRAM check routines copied from gw8260 */
620 #if defined (CONFIG_SYS_DRAM_TEST)
622 /*********************************************************************/
623 /* NAME: move64() - moves a double word (64-bit) */
626 /* this function performs a double word move from the data at */
627 /* the source pointer to the location at the destination pointer. */
630 /* unsigned long long *src - pointer to data to move */
633 /* unsigned long long *dest - pointer to locate to move data */
638 /* RESTRICTIONS/LIMITATIONS: */
639 /* May cloober fr0. */
641 /*********************************************************************/
642 static void move64 (unsigned long long *src, unsigned long long *dest)
644 asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
645 "stfd 0, 0(4)" /* *dest = fpr0 */
646 : : : "fr0"); /* Clobbers fr0 */
651 #if defined (CONFIG_SYS_DRAM_TEST_DATA)
653 unsigned long long pattern[] = {
654 0xaaaaaaaaaaaaaaaaLL,
655 0xccccccccccccccccLL,
656 0xf0f0f0f0f0f0f0f0LL,
657 0xff00ff00ff00ff00LL,
658 0xffff0000ffff0000LL,
659 0xffffffff00000000LL,
660 0x00000000ffffffffLL,
661 0x0000ffff0000ffffLL,
662 0x00ff00ff00ff00ffLL,
663 0x0f0f0f0f0f0f0f0fLL,
664 0x3333333333333333LL,
665 0x5555555555555555LL,
668 /*********************************************************************/
669 /* NAME: mem_test_data() - test data lines for shorts and opens */
672 /* Tests data lines for shorts and opens by forcing adjacent data */
673 /* to opposite states. Because the data lines could be routed in */
674 /* an arbitrary manner the must ensure test patterns ensure that */
675 /* every case is tested. By using the following series of binary */
676 /* patterns every combination of adjacent bits is test regardless */
679 /* ...101010101010101010101010 */
680 /* ...110011001100110011001100 */
681 /* ...111100001111000011110000 */
682 /* ...111111110000000011111111 */
684 /* Carrying this out, gives us six hex patterns as follows: */
686 /* 0xaaaaaaaaaaaaaaaa */
687 /* 0xcccccccccccccccc */
688 /* 0xf0f0f0f0f0f0f0f0 */
689 /* 0xff00ff00ff00ff00 */
690 /* 0xffff0000ffff0000 */
691 /* 0xffffffff00000000 */
693 /* The number test patterns will always be given by: */
695 /* log(base 2)(number data bits) = log2 (64) = 6 */
697 /* To test for short and opens to other signals on our boards. we */
699 /* test with the 1's complemnt of the paterns as well. */
702 /* Displays failing test pattern */
705 /* 0 - Passed test */
706 /* 1 - Failed test */
708 /* RESTRICTIONS/LIMITATIONS: */
709 /* Assumes only one one SDRAM bank */
711 /*********************************************************************/
712 int mem_test_data (void)
714 unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
715 unsigned long long temp64 = 0;
716 int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
720 for (i = 0; i < num_patterns; i++) {
721 move64 (&(pattern[i]), pmem);
722 move64 (pmem, &temp64);
724 /* hi = (temp64>>32) & 0xffffffff; */
725 /* lo = temp64 & 0xffffffff; */
726 /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
728 hi = (pattern[i] >> 32) & 0xffffffff;
729 lo = pattern[i] & 0xffffffff;
730 /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */
732 if (temp64 != pattern[i]) {
733 printf ("\n Data Test Failed, pattern 0x%08x%08x",
741 #endif /* CONFIG_SYS_DRAM_TEST_DATA */
743 #if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
744 /*********************************************************************/
745 /* NAME: mem_test_address() - test address lines */
748 /* This function performs a test to verify that each word im */
749 /* memory is uniquly addressable. The test sequence is as follows: */
751 /* 1) write the address of each word to each word. */
752 /* 2) verify that each location equals its address */
755 /* Displays failing test pattern and address */
758 /* 0 - Passed test */
759 /* 1 - Failed test */
761 /* RESTRICTIONS/LIMITATIONS: */
764 /*********************************************************************/
765 int mem_test_address (void)
767 volatile unsigned int *pmem =
768 (volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
769 const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
772 /* write address to each location */
773 for (i = 0; i < size; i++) {
777 /* verify each loaction */
778 for (i = 0; i < size; i++) {
780 printf ("\n Address Test Failed at 0x%x", i);
786 #endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
788 #if defined (CONFIG_SYS_DRAM_TEST_WALK)
789 /*********************************************************************/
790 /* NAME: mem_march() - memory march */
793 /* Marches up through memory. At each location verifies rmask if */
794 /* read = 1. At each location write wmask if write = 1. Displays */
795 /* failing address and pattern. */
798 /* volatile unsigned long long * base - start address of test */
799 /* unsigned int size - number of dwords(64-bit) to test */
800 /* unsigned long long rmask - read verify mask */
801 /* unsigned long long wmask - wrtie verify mask */
802 /* short read - verifies rmask if read = 1 */
803 /* short write - writes wmask if write = 1 */
806 /* Displays failing test pattern and address */
809 /* 0 - Passed test */
810 /* 1 - Failed test */
812 /* RESTRICTIONS/LIMITATIONS: */
815 /*********************************************************************/
816 int mem_march (volatile unsigned long long *base,
818 unsigned long long rmask,
819 unsigned long long wmask, short read, short write)
822 unsigned long long temp = 0;
823 unsigned int hitemp, lotemp, himask, lomask;
825 for (i = 0; i < size; i++) {
827 /* temp = base[i]; */
828 move64 ((unsigned long long *) &(base[i]), &temp);
830 hitemp = (temp >> 32) & 0xffffffff;
831 lotemp = temp & 0xffffffff;
832 himask = (rmask >> 32) & 0xffffffff;
833 lomask = rmask & 0xffffffff;
835 printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
840 /* base[i] = wmask; */
841 move64 (&wmask, (unsigned long long *) &(base[i]));
846 #endif /* CONFIG_SYS_DRAM_TEST_WALK */
848 /*********************************************************************/
849 /* NAME: mem_test_walk() - a simple walking ones test */
852 /* Performs a walking ones through entire physical memory. The */
853 /* test uses as series of memory marches, mem_march(), to verify */
854 /* and write the test patterns to memory. The test sequence is as */
856 /* 1) march writing 0000...0001 */
857 /* 2) march verifying 0000...0001 , writing 0000...0010 */
858 /* 3) repeat step 2 shifting masks left 1 bit each time unitl */
859 /* the write mask equals 1000...0000 */
860 /* 4) march verifying 1000...0000 */
861 /* The test fails if any of the memory marches return a failure. */
864 /* Displays which pass on the memory test is executing */
867 /* 0 - Passed test */
868 /* 1 - Failed test */
870 /* RESTRICTIONS/LIMITATIONS: */
873 /*********************************************************************/
874 int mem_test_walk (void)
876 unsigned long long mask;
877 volatile unsigned long long *pmem =
878 (volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
879 const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
885 printf ("Initial Pass");
886 mem_march (pmem, size, 0x0, 0x1, 0, 1);
888 printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
891 printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
893 for (i = 0; i < 63; i++) {
894 printf ("Pass %2d", i + 2);
895 if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
896 /*printf("mask: 0x%x, pass: %d, ", mask, i); */
900 printf ("\b\b\b\b\b\b\b");
903 printf ("Last Pass");
904 if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
905 /* printf("mask: 0x%x", mask); */
908 printf ("\b\b\b\b\b\b\b\b\b");
910 printf ("\b\b\b\b\b\b\b\b\b");
915 /*********************************************************************/
916 /* NAME: testdram() - calls any enabled memory tests */
919 /* Runs memory tests if the environment test variables are set to */
923 /* testdramdata - If set to 'y', data test is run. */
924 /* testdramaddress - If set to 'y', address test is run. */
925 /* testdramwalk - If set to 'y', walking ones test is run */
931 /* 0 - Passed test */
932 /* 1 - Failed test */
934 /* RESTRICTIONS/LIMITATIONS: */
937 /*********************************************************************/
944 #ifdef CONFIG_SYS_DRAM_TEST_DATA
945 rundata = getenv_yesno("testdramdata") == 1;
947 #ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
948 runaddress = getenv_yesno("testdramaddress") == 1;
950 #ifdef CONFIG_SYS_DRAM_TEST_WALK
951 runwalk = getenv_yesno("testdramwalk") == 1;
954 if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
955 printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
957 #ifdef CONFIG_SYS_DRAM_TEST_DATA
959 printf ("Test DATA ... ");
960 if (mem_test_data () == 1) {
961 printf ("failed \n");
967 #ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
968 if (runaddress == 1) {
969 printf ("Test ADDRESS ... ");
970 if (mem_test_address () == 1) {
971 printf ("failed \n");
977 #ifdef CONFIG_SYS_DRAM_TEST_WALK
979 printf ("Test WALKING ONEs ... ");
980 if (mem_test_walk () == 1) {
981 printf ("failed \n");
987 if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
993 #endif /* CONFIG_SYS_DRAM_TEST */
995 /* ronen - the below functions are used by the bootm function */
996 /* - we map the base register to fbe00000 (same mapping as in the LSP) */
997 /* - we turn off the RX gig dmas - to prevent the dma from overunning */
998 /* the kernel data areas. */
999 /* - we diable and invalidate the icache and dcache. */
1000 void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
1004 temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
1005 if ((temp & 0xffff) == new_loc >> 16)
1008 temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
1009 0xffff0000) | (new_loc >> 16);
1011 out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
1013 while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
1015 (INTERNAL_SPACE_DECODE)))))
1020 void board_prebootm_init ()
1023 /* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */
1024 GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16);
1026 /* Stop GigE Rx DMA engines */
1027 GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00);
1028 /* GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00); */
1029 /* GV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00); */
1031 /* Relocate MV64360 internal regs */
1032 my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, CONFIG_SYS_DFL_GT_REGS);
1038 int do_show_config(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
1040 unsigned int reset_sample_low;
1041 unsigned int reset_sample_high;
1042 unsigned int l, l1, l2;
1044 GT_REG_READ(0x3c4, &reset_sample_low);
1045 GT_REG_READ(0x3d4, &reset_sample_high);
1046 printf("Reset configuration 0x%08x 0x%08x\n", reset_sample_low, reset_sample_high);
1049 for (l=0; l<63; l++) {
1050 if (show_config_tab[l][0] != 0) {
1051 printf("%14s:%1x ", show_config_tab[l],
1052 ((reset_sample_low >> (31 - (l & 0x1f)))) & 0x01);
1060 reset_sample_low = reset_sample_high;
1068 show_config, 1, 1, do_show_config,
1069 "Show Marvell strapping register",
1070 "Show Marvell strapping register (ResetSampleLow ResetSampleHigh)"
1073 int do_pldver(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
1075 printf("PLD version:0x%02x\n", in_8((void *)CONFIG_SYS_PLD_VER));
1081 pldver, 1, 1, do_pldver,
1083 "Show PLD version)");
1085 int board_eth_init(bd_t *bis)
1087 return mv6436x_eth_initialize(bis);